MC14LC5480DWR2 Freescale Semiconductor, MC14LC5480DWR2 Datasheet - Page 13
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MC14LC5480DWR2
Manufacturer Part Number
MC14LC5480DWR2
Description
IC 5V PCM CODEC-FILTER 20-SOIC W
Manufacturer
Freescale Semiconductor
Type
PCM Codec/Filterr
Datasheet
1.MC14LC5480DWR2.pdf
(24 pages)
Specifications of MC14LC5480DWR2
Data Interface
PCM Audio Interface
Resolution (bits)
13 b
Number Of Adcs / Dacs
1 / 1
Sigma Delta
No
Voltage - Supply, Digital
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (0.300", 7.50mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
MC14LC5480DWTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC14LC5480DWR2
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
DIGITAL SWITCHING CHARACTERISTICS, LONG FRAME SYNC AND SHORT FRAME SYNC
(V DD = + 5 V
Ref.
No.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1
1
2
3
4
5
6
7
8
9
Master Clock Frequency for MCLK
MCLK Duty Cycle for 256 kHz Operation
Minimum Pulse Width High for MCLK (Frequencies of 512 kHz or Greater)
Minimum Pulse Width Low for MCLK (Frequencies of 512 kHz or Greater)
Rise Time for All Digital Signals
Fall Time for All Digital Signals
Setup Time from MCLK Low to FST High
Setup Time from FST High to MCLK Low
Bit Clock Data Rate for BCLKT or BCLKR
Minimum Pulse Width High for BCLKT or BCLKR
Minimum Pulse Width Low for BCLKT or BCLKR
Hold Time from BCLKT (BCLKR) Low to FST (FSR) High
Setup Time for FST (FSR) High to BCLKT (BCLKR) Low
Setup Time from DR Valid to BCLKR Low
Hold Time from BCLKR Low to DR Invalid
Hold Time from 2nd Period of BCLKT (BCLKR) Low to FST (FSR) Low
Delay Time from FST or BCLKT, Whichever is Later, to DT for Valid MSB Data
Delay Time from BCLKT High to DT for Valid Chord and Step Bit Data
Delay Time from the Later of the 8th BCLKT Falling Edge, or the Falling Edge
of FST to DT Output High Impedance
Minimum Pulse Width Low for FST or FSR
Hold Time from BCLKT (BCLKR) Low to FST (FSR) Low
Setup Time from FST (FSR) Low to MSB Period of BCLKT (BCLKR) Low
Delay Time from BCLKT High to DT Data Valid
Delay Time from the 8th BCLKT Low to DT Output High Impedance
5%, V SS = 0 V, All Digital Signals Referenced to V SS , T A = – 40 to + 85 C, C L = 150 pF, Unless Otherwise Noted)
Freescale Semiconductor, Inc.
For More Information On This Product,
Characteristics
Go to: www.freescale.com
SHORT FRAME SPECIFIC TIMING
LONG FRAME SPECIFIC TIMING
Min
45
50
50
50
50
64
50
50
20
80
50
50
10
50
50
50
10
10
—
—
—
—
—
—
—
—
—
—
—
0
1536
1544
2048
2560
4096
Typ
256
512
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4096
Max
—
—
—
—
—
—
—
55
—
—
50
50
—
—
—
—
—
—
—
—
—
60
60
60
—
—
—
60
60
Unit
kHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%