LM4546VH National Semiconductor, LM4546VH Datasheet - Page 13

• Manufacturer Part Number: LM4546VH
• Description: IC AUDIO CODEC '97 18BIT 48LQFP
• Manufacturer: National Semiconductor
• Type: Audio Codec '97r

Specifications of LM4546VH

• Data Interface: Serial
• Resolution (bits): 18 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 89
• Voltage - Supply, Analog: 4.2 V ~ 5.5 V
• Voltage - Supply, Digital: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *LM4546VH

SDATA_OUT Slot 1: Control Address
Slot 1 is used both to write to the LM4546 registers as well as
read back a register's current value. The MSB of Slot 1 (bit
19) signifies whether the current control operation is a read
or a write. Bits 18 through 12 are used to specify the register
address of the read or write operation. The least significant
twelve bits are reserved and should be stuffed with zeros by
the AC'97 controller.
SDATA_OUT Slot 2: Control Data
Slot 2 is used to transmit 16 bit control data to the LM4546 in
the event that the current operation is a write operation. The
least significant four bits should be stuffed with zeros by the
AC Link Input Frame: SDATA_IN (input to controller,
output from LM4546)
The audio input frame (input to the AC '97 Digital Controller)
contains status and PCM data from the LM4546 control reg-
isters and stereo ADC. The Tag slot, slot 0, contains 16 bits
that tell the AC '97 Digital Controller whether the LM4546 is
ready and the validity of data from certain device subsections.
A new audio input frame is signaled with a low to high transi-
tion of SYNC. SYNC is synchronous to the rising edge of
BIT_CLK. On the next rising edge of BIT_CLK, the LM4546
drives SDATA_IN with the first bit of slot 0. The Digital Con-
troller samples SDATA_IN on the falling edge of BIT_CLK.
The LM4546 will continue outputting the SDATA_IN stream
on each successive rising edge of BIT_CLK. The LM4546
outputs data MSB first, in a MSB justified format. All reserved
bits and slots are stuffed with "0" 's by the LM4546.
18:12
11:0
Bits
Bit
15
14
13
12
11
19
Control Register
Control register
Control register
Right Playback
Left Playback
Description
Description
Valid Frame
Read/Write
PCM Data
PCM Data
Reserved
address
data
1 = Control Address is valid.
1 = Right PCM Data is valid.
1 = Left PCM Data is valid.
1 = Control Data is valid.
1 = This frame has valid
Identifies the Control
1 = Read, 0 = Write
100985 Version 4 Revision 1
Comment
Comment
Set to "0"
Register
data.
FIGURE 6. AC Link Audio Input Frame
Print Date/Time: 2009/04/29 09:52:43
13
AC '97 controller. If the current operation is a register read,
the entire slot, bits 19 through 0 should be stuffed with zeros.
SDATA_OUT Slot 3: PCM Playback Left Channel
Slot 3 is a 20 bit field used to transmit data intended for the
left DAC on the LM4546. Any unused bits should be padded
with zeros. The LM4546 DACs have 18 bit resolution and thus
will use the first 18 bits of the 20 bit PCM stream.
SDATA_OUT Slot 4: PCM Playback Right Channel
Slot 4 is a 20 bit field used to transmit data intended for the
right DAC on the LM4546. Any unused bits should be padded
with zeros. The LM4546 DACs have 18 bit resolution and thus
will use the first 18 bits of the 20 bit PCM stream.
SDATA_OUT Slots 5-12: Reserved
Set these SDATA_OUT slots to "0" as they are not currently
implemented and are reserved for future use.
SDATA_IN Slot 0: Codec Status Bits
The first bit of SDATA_IN Slot 0 (bit 15) indicates when the
Codec is ready. The digital controller must probe further to
see which other subsections are ready.
19:4
19:0
19:0
Bits
Bits
Bits
3:0
Control Register
Data for Right
Description
Description
Data for Left
Description
PCM Audio
PCM Audio
Write Data
Reserved
DAC
DAC
Set unused bits to "0"
Set unused bits to "0"
Set bits to "0" if read
Comment
Comment
Comment
operation
Set to "0"
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