AD1888JST Analog Devices Inc, AD1888JST Datasheet - Page 27

• Manufacturer Part Number: AD1888JST
• Description: IC CODEC AUDIO-PC AC'97 48LQFP
• Manufacturer: Analog Devices Inc
• Series: SoundMAX®r
• Type: Audio Codec '97r

Specifications of AD1888JST

• Data Interface: Serial
• Resolution (bits): 16, 20 b
• Number Of Adcs / Dacs: 2 / 6
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 80 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3.15/4.75V
• Single Supply Voltage (max): 3.45/5.25V
• Package Type: LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 42. Serial Configuration Register (Index 74h)
Reg
No.
74h
SPLNK
SPDZ
SPAL
INTS
LBKS[1:0]
CHEN
DRF
REGM3
REGM0
REGM1
REGM2
SLOT16
Name
Serial
Config
SPDIF Link. This bit enables the SPDIF to link with the front DACs for data requesting.
0 = SPDIF and DAC are not linked.
1 = SPDIF and DAC are linked and receive the same data requests (reset default).
SPDIF DACZ.
0 = Repeat last sample out of the SPDIF stream if FIFO underruns (reset default).
1 = Forces midscale sample out the SPDIF stream if FIFO underruns.
SPDIF ADC Loop-Around.
0 = SPDIF transmitter is connected to the AC-Link stream (reset default).
1= SPDIF transmitter is connected to the digital ADC stream, not the AC-Link.
Interrupt Mode Select. This bit selects the JS interrupt implementation path.
1 = Slot 6 Valid Bit (MIC ADC interrupt).
Loop-Back Selection. These bits select the internal digital loop-back path when LPBK bit is active (see Register 20h)
00 = Loop-back through the front DACs (reset default).
01 = Loop-back through the surround DACs.
10 = Reserved
11 = Loop-back through the center and LFE DACs (center DAC loops back from the ADC left channel, the LFE DAC from the ADC
right channel).
Chain Enable. This bit enables chaining of a slave codec SDATA_IN stream into the ID0 pin (Pin 45).
0 = Disable chaining (reset default).
1 = Enable chaining into ID0 pin.
DAC Request Force. This allows the AD1888 to synchronize DAC requests with the AD1981A/B.
0 = Normal DAC requesting sequence (reset default).
1 = Synchronize to AD1981A/B DAC requests.
Slave 3 Codec Register Mask
Master Codec Register Mask
Slave 1 Codec Register Mask
Slave 2 Codec Register Mask
Enable 16-Bit Slot Mode. SLOT16 makes all ac-link slots 16 bits in length, formatted into 16 slots. This is a preferred mode for
DSP serial port interfacing.
0 = Bit 0 SLOT 12 (modem interrupt) (reset default).
D15
SLOT16
D14
REGM2
D13
REGM1
D12
REGM0
D11
REGM3
D10
DRF
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D9
X
D8
CHEN
D7
X
D6
LBKS1
D5
LBKS0
D4
INTS
D3
X
D2
SPAL
D1
SPDZ
D0
SPLNK
AD1888
Default
1001h