AD1985JST Analog Devices Inc, AD1985JST Datasheet - Page 38

• Manufacturer Part Number: AD1985JST
• Description: IC CODEC STEREO 6-DAC 20B 48LQFP
• Manufacturer: Analog Devices Inc
• Series: SoundMAX®r
• Type: Audio Codec '97r

Specifications of AD1985JST

• Rohs Status: RoHS non-compliant
• Data Interface: Serial
• Resolution (bits): 16, 20 b
• Number Of Adcs / Dacs: 2 / 6
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 84 / 90
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.97 V ~ 3.63 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP

Reg
Num
0x74
AD1985
Serial Configuration (Index 0x74)
Note: This register will only reset bits CSWP (D3), LBKS[1:0] (D[6:5]), and OMS (D9) when Register 0x00 is written to (soft reset). All bits are reset on a hard or hardware
reset.
SPLNK
SPDZ
SPAL
CSWP
INTS
LBKS[1:0]
SPOVR
CHEN
OMS
DRF
REGM3
REGM0
REGM1
REGM2
SLOT16
Name
Serial
Config.
SPDIF Link. This bit enables the SPDIF to link with the front DACs for data requesting.
0: SPDIF and front DACs are not linked.
1: SPDIF and front DACs are linked and receive same data requests. (Reset default.)
SPDIF DACZ.
0: Repeat last sample out the SPDIF stream if FIFO underruns. (Reset default.)
1: Forces midscale sample out the SPDIF stream if FIFO underruns.
SPDIF ADC Loop-Around.
0: SPDIF transmitter is connected to the AC Link stream. (Reset default.)
1: SPDIF transmitter is connected to the digital ADC stream, not the AC Link.
Swap the Center/LFE Channels. Some systems have a swapped external connection for the center and LFE Channels.
Setting this bit will swap these channels internal to the codec. Setting this bit also swaps the definitions of the center/LFE
volume controls in Register 0x36.
Interrupt Mode Select. This bit selects the audio interrupt implementation path.
0: Slot 12, Bit 0 (modem interrupt) (reset default).
1: Slot 6, Valid Bit (MIC ADC interrupt).
Note: This bit does not generate an interrupt. Rather, it steers the path of the generated interrupt.
Loop-Back Selection. These bits select the internal digital loop-back path when the LPBK bit is active (see Register 0x20).
00: Loop back through the front DACs. (Reset default.)
01: Loop back through the surround DACs.
11: Loop back through the center and LFE DACs. (Center DAC loops back from the ADC left channel, the LFE DAC from the
10: Reserved.
SPDIF Override.
0: SPDIF Transmitter is enabled only if the SPDIF pin is pulled low on reset. (Reset default.)
1: SPDIF Transmitter is enabled regardless of the SPDIF pin configuration.
Chain Enable. This bit enables chaining of a slave codec SDATA_IN stream into the ID0 pin (Pin 45).
0: Disable chaining. (Reset default.)
1: Enable chaining into ID0 pin.
Output Microphone Select. This bit will switch the microphone inputs between the MIC1/MIC2 pins and the Center/LFE
pins. This feature is used for those systems that have input/output jack sharing.
Note: See the charts describing the microphone inputs—the description of MS (Bit D8, Register 0x20) and the record
select control register (0x1A).
0: Microphone inputs come from MIC1 and MIC2 pins. Center/LFE outputs behave as expected (default).
1: Microphone inputs now come from the Center/LFE pins. The codec will place the Center/LFE outputs into a High-Z
state—equivalent to setting CLDIS (Bit D11, Register 0x76). Setting the OMS bit, however, will not overwrite the CLDIS;
Center/LFE outputs respond equally to both bits.
DAC Request Force: This allows the AD1985 to synchronize DAC requests with the AD1981A/ AD1981B.
0: Normal DAC requesting sequence. (Reset default.)
1: Synchronize to AD1981A/B DAC requests.
Slave 3 Codec Register Mask.
Master Codec Register Mask. (Reset default.)
Slave 1 Codec Register Mask.
Slave 2 Codec Register Mask.
Enable 16-Bit Slot Mode. SLOT16 makes all AC Link slots 16 bits in length, formatted into 16 slots. This is a preferred mode
for DSP serial port interfacing.
D15
SLOT16 REGM2 REGM1 REGM0 REGM3 DRF OMS CHEN SPOVR LBKS1 LBKS0 INTS CSWP SPAL SPDZ SPLNK 0x1001
ADC right channel.)
D14
D13
D12
D11
Rev. A | Page 38 of 48
D10 D9
D8
D7
D6
D5
D4 D3
D2
D1
D0
Default