MAX9853ETM+ Maxim Integrated Products, MAX9853ETM+ Datasheet - Page 15

• Manufacturer Part Number: MAX9853ETM+
• Description: IC CODEC AUDIO STEREO 48TQFN
• Manufacturer: Maxim Integrated Products
• Type: Stereo Audior

Specifications of MAX9853ETM+

• Data Interface: Serial
• Resolution (bits): 18 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 81.5 / 88
• Dynamic Range, Adcs / Dacs (db) Typ: 82 / 87.5
• Voltage - Supply, Analog: 2.6 V ~ 3.3 V
• Voltage - Supply, Digital: 1.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Conversion Rate: 48 KHz
• Resolution: 18 bit
• Operating Supply Voltage: 1.7 V to 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Snr: 75 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS (continued)
(AV
10kΩ, R
PGAs = 0dB, HP/REC volume = -20.0dB, SPK volume = -20.4dB, line output gain = -0.4dB, T
noted. Typical values are at T
Stereo Audio CODECs with Microphone, DirectDrive
VOICE MODE TIMING CHARACTERISTICS (Digital Audio Interface S1 and S2)
BCLK_ Cycle Time
BCLK_ High Time
BCLK_ Low Time
BCLK_ or LRCLK_ Rise and Fall
Time
SDIN_ or LRCLK_ to BCLK_
Rising Edge Setup Time
SDIN_ or LRCLK_ to BCLK_
Rising Edge Hold Time
SDOUTS1 Delay Time
SDOUTS2 Delay Time
OPEN-DRAIN DIGITAL OUTPUTS (SDA, IRQ)
Output High Current
Output Low Voltage
OPEN-DRAIN DIGITAL OUTPUT (SHDNOUT) (MAX9853 Only)
Output High Current
Output Low Voltage
I
Serial Clock Frequency
Bus Free Time Between STOP
and START Conditions
Hold Time (Repeated) START
Condition
SCL Pulse Width Low
SCL Pulse Width High
Setup Time for a Repeated
START Condition
2
C TIMING CHARACTERISTICS
DD
Headphones, Speaker Amplifiers, or Line Outputs
= CPV
OUTR+
PARAMETER
DD
to R
= +3V, DV
OUTR-
______________________________________________________________________________________
= 10kΩ, C1 = 0.22µF, C2 = C
DD
A
= DV
= +25°C.) (See Functional Diagrams/Typical Operating Circuits).
DDS2
SYMBOL
t
t
HD,STA
SU,STA
t
t
t
t
f
t
HIGH
V
V
I
I
LOW
t
t
t
t
t
t
DLY
DLY
SCL
BUF
OH
OH
BC
BH
r,
HD
BL
SU
= +1.8V, PV
OL
OL
t
f
Master mode, C
BCI = 0 (see I
BCI = 0 (see I
BCI = 0 (see I
from BCLK rising edge
BCI = 0 (see I
from BCLK rising edge
V
I
I
V
I
OL
OL
OL
OUT
OUT
= 3mA for DV
= 3mA for DV
= 100µA
DD
= DV
= DV
NREG
= +3.3V, R
DD
DD
= C
2
2
2
2
C register definition)
C register definition)
C register definition),
C register definition),
CONDITIONS
LOAD
PREG
DD
DD
HP
> 2V
< 2V
= 32Ω, Z
= 15pF
= C
INTMICBIAS
SPK
= 8Ω + 10µH, R
, C
MBIAS
A
= C
MIN
1.3
0.6
1.3
0.6
0.6
75
30
30
30
= T
5
0
REC
REF
MIN
= 32Ω, R
= 1µF, MCLK = 13MHz, all
to T
TYP
7
MAX
OUTL+
, unless otherwise
DV
MAX
0.2 x
400
0.4
0.4
35
50
3
3
DD
to R
UNITS
OUTL-
kHz
µA
µA
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
V
V
15
=