EMC2305-1-AP-TR SMSC, EMC2305-1-AP-TR Datasheet - Page 21

• Manufacturer Part Number: EMC2305-1-AP-TR
• Description: Industrial Temperature Sensors Penta RPM-Based PWN Fan Speed Controller
• Manufacturer: SMSC

Specifications of EMC2305-1-AP-TR

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Multiple RPM-Based PWM Fan Controller for Five Fans
Datasheet
SMSC EMC2305
4.4.2
4.5
4.5.1
4.5.2
If the RPM-based Fan Speed Control Algorithm is enabled, the algorithm will automatically attempt to
restart the fan until it detects a valid tachometer level or is disabled.
The FAN_STALL Status bit indicates that a stalled fan was detected. This bit is checked conditionally
depending on the mode of operation.
Aging Fan or Invalid Drive Detection
This is useful to detect aging fan conditions (where the fan’s natural maximum speed degrades over
time) or a speed setting that is faster than the fan is capable of. The EMC2305 contains circuitry that
detects that the programmed fan speed can be reached by the fan. If the target fan speed cannot be
reached within a user defined band of tach counts at maximum drive, the DRIVE_FAIL status bits are
set and the ALERT# pin is asserted.
The CLK pin has multiple functionality as determined by the pull-up decode of the ADDR_SEL pin and
the settings of the Configuration register. The functionality associated with the CLK pin upon device
power up is independent of the CLK pin functionality after the device has been configured.
Pull Up Decode
If additional functionality is enabled via the ADDR_SEL pin (see
should be configured with a pull-up resistor to VDD and should not be used. The value of the pull-up
resistor on the CLK pin is used to determine the default drive state of all fan drivers as shown in
Table
External Clock
The EMC2305 allows the user to choose between supplying an external 32.768kHz clock or use of
the internal 32kHz oscillator to measure the tachometer signal. This clock source is used by the RPM-
based Fan Speed Control Algorithm to calculate the current fan speed. This fan controller accuracy is
directly proportional to the accuracy of the clock source.
When this function is used, the external clock is driven into the device via the CLK pin.
CLK Pin
Whenever the Direct Setting Mode or the Spin Up Routine is enabled, the FAN_STALL interrupt
will be masked for the duration of the programmed Spin Up Time (see
to reach a valid speed without generating unnecessary interrupts.
In Direct Setting Mode, whenever the TACH Reading Register value exceeds the Valid TACH Count
Register setting, the FAN_STALL status bit will be set.
When using the RPM-based Fan Speed Control Algorithm, the stalled fan condition is checked
whenever the Update Time is met and the fan drive setting is updated. It is not a continuous check.
PULL-UP RESISTOR
4.2.
4.7k Ohm ±5%
6.8k Ohm ±5%
10k Ohm ±5%
15k Ohm ±5%
22k Ohm ±5%
33k Ohm ±5%
Table 4.2 CLK Pin Pull-Up Decode
DATASHEET
21
FAN DEFAULT DRIVE SETTING
Section
0% - OFF
0% - OFF
100%
30%
50%
75%
Table
3.1.2), then the CLK pin
5.22) to allow the fan
Revision 1.2 (03-22-10)