EMC2101-ACZL-TR SMSC, EMC2101-ACZL-TR Datasheet - Page 22
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EMC2101-ACZL-TR
Manufacturer Part Number
EMC2101-ACZL-TR
Description
Industrial Temperature Sensors Sngl Fan Contrllr
Manufacturer
SMSC
Datasheet
1.EMC2101-ACZL.pdf
(57 pages)
Specifications of EMC2101-ACZL-TR
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Part Number:
EMC2101-ACZL-TR
Manufacturer:
SMSC
Quantity:
20 000
Revision 2.54 (06-16-09)
5.4.2
5.4.3
5.5
Δ
V
BE
=
ALERT / TACH as an Interrupt
When the ALERT / TACH pin is used as an interrupt signal the pin is asserted whenever an out-of-
limit condition is detected. The ALERT / TACH pin will remain asserted until it is cleared even if the
error condition is removed.
Mask Bit
The MASK bit behaves differently depending on which mode the ALERT / TACH pin is configured to
operate in.
If the EMC2101 is configured with the ALERT / TACH pin operating in Interrupt Mode, the MASK bit
will be set in the following cases:
1. Automatically after the Status Register has been read if any bits in the Status Register have been
2. Automatically when the EMC2101 responds to an Alert Response Address (ARA) command on an
3. Directly via the SMBus.
In Interrupt Mode, the MASK bit will block the ALERT / TACH pin from being asserted in response to
an error condition.
If the EMC2101 is configured with the ALERT / TACH pin operating in Comparator Mode, the MASK
bit can only be set via the SMBus. In this mode, setting the MASK bit willl not affect the ALERT / TACH
pin.
In either mode, setting the individual channel mask bits will block the appropriate channel from
asserting the ALERT / TACH pin.
In general, thermal diode temperature measurements are based on the change in forward bias voltage
of a diode when operated at two different currents. The change in forward bias voltage is proportional
to absolute temperature (T).
Temperature Monitors
V
BE
set (except BUSY and FAULT) (See
SMBus and the ALERT / TACH pin is asserted. The ARA command does not clear the Status
Register. If the MASK bit is cleared prior to reading and clearing the Status Register, then the
ALERT / TACH pin will be asserted.
_
HIGH
−
V
BE
_
LOW
=
η
kT
q
ln
⎛
⎜ ⎜
⎝
DATASHEET
I
I
HIGH
LOW
Table
22
⎞
⎟ ⎟
⎠
SMBus Fan Control with 1°C Accurate Temperature Monitoring
6.3).
Where:
k = Boltzmann’s constant
T = Absolute Temperature in Kelvin
q = electron charge
η
= Diode Ideality Factor
SMSC EMC2101
Eq: [1]
Datasheet