LM4549BVHX/NOPB National Semiconductor, LM4549BVHX/NOPB Datasheet
LM4549BVHX/NOPB
Specifications of LM4549BVHX/NOPB
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LM4549BVHX/NOPB Summary of contents
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... Output Frames. The AC ’97 architecture separates the analog and digital functions of the PC audio system allowing both for system design flexibility and increased performance. © 2006 National Semiconductor Corporation Key Specifications n Analog Mixer Dynamic Range n DAC Dynamic Range n ADC Dynamic Range Features n AC ’ ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage Storage Temperature Input Voltage ESD Susceptibility (Note 2) pin 3 ESD Susceptibility (Note 3) pin 3 Junction Temperature Electrical Characteristics 48 kHz, single codec configuration, (primary mode) unless otherwise noted. Limits apply for Vrms unless otherwise specified ...
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Electrical Characteristics 48 kHz, single codec configuration, (primary mode) unless otherwise noted. Limits apply for Vrms unless otherwise specified. (Continued) Symbol Parameter Analog to Digital Converters Resolution Dynamic Range (Note 9) Frequency Response Digital to Analog Converters ...
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Electrical Characteristics 48 kHz, single codec configuration, (primary mode) unless otherwise noted. Limits apply for Vrms unless otherwise specified. (Continued) Symbol Parameter Hold Time for codec SYNC T SHOLD inpu(Note 9)t T Output Valid Delay CO T ...
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Timing Diagrams Clocks Digital Rise and Fall www.national.com Data Delay, Setup and Hold 20123510 20123512 Power On Reset Cold Reset Warm Reset 6 20123511 Legend 20123530 20123529 20123513 20123514 ...
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Typical Application FIGURE 1. LM4549B Typical Application Circuit, Single Codec, 1 Vrms inputs APPLICATION HINTS • The LM4549B must be initialized by using RESET# to perform a Power On Reset as shown in the Power On Reset Timing Diagram • ...
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Connection Diagram Pin Descriptions Name Pin Functional Description Mono Input This line level (1 Vrms nominal) mono input is mixed equally into both channels of the Stereo Mix signal at MIX2 under the control of the PC_Beep ...
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Pin Descriptions (Continued) Name Pin Functional Description Left Stereo Channel Input This line level input (1 Vrms nominal) is selectable at the left channel of the stereo Record Select Mux for conversion by the left channel ADC. ...
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Pin Descriptions (Continued) Name Pin Functional Description Mono microphone input Either MIC1 or MIC2 can be muxed to a programmable boost amplifier with selection by the MS bit (bit D8) in the General Purpose register, 20h. The ...
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Pin Descriptions (Continued) Name Pin Functional Description Left Stereo Channel Output This line level output (1 Vrms nominal) is fed from the left channel of the Stereo Mix signal LNLVL_OUT_L 39 O from MIX2 via the Line ...
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Pin Descriptions (Continued) Name Pin Cold Reset This active low signal causes a hardware reset which returns the control registers and all internal circuits to their default conditions. RESET# MUST be used to initialize the LM4549B RESET# ...
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Pin Descriptions (Continued) Name Pin 29, 30 31, 32 These pins are not used and should be left open (NC For second source applications these pins may be connected to a noise-free supply ...
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Volume Output Volume Input Sources ADC 15 www.national.com ...
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Functional Description GENERAL The LM4549B codec can mix, process and convert among analog (stereo and mono) and digital (AC Link format) inputs and outputs. There are four stereo and four mono analog inputs and two stereo and one mono analog ...
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Functional Description REGISTER RESET is performed when any value is written to the RESET register, 00h. It resets all registers to their AC Link Serial Interface Protocol AC LINK OUTPUT FRAME: SDATA_OUT, CONTROLLER OUTPUT TO LM4549B INPUT The AC Link ...
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AC Link Serial Interface Protocol (Continued) SDATA_OUT: Slot 0 – Tag Phase The first bit of Slot 0 is designated the "Valid Frame" bit. If this bit indicates that the current Output Frame con- tains at least ...
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AC Link Serial Interface Protocol (Continued) SLOTS 3 & 4, OUTPUT FRAME Bits Description Comment Slots used to stream data to PCM DAC Data DACs for all Primary or 19:0 (Left /Right Secondary modes. Channels) Set unused bits to "0" ...
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AC Link Serial Interface Protocol (Continued) check the status of these subsections after Initialization, Cold Reset, or the use of the powerdown modes in order to minimize the risk of distorting analog signals passed before the subsections are ready. The ...
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AC Link Serial Interface Protocol (Continued) SLOT 3, INPUT FRAME (Continued) Bits Description Comment 1:0 Reserved Stuffed with "0"s by LM4549B SDATA_IN: Slot 4 – PCM Record Right Channel This slot contains sampled data from the right channel of the ...
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Register Descriptions Default settings are indicated by *. RESET REGISTER (00h) Writing any value to this register causes a Register Reset which changes all registers back to their default values read is performed on this register, the LM4549B ...
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Register Descriptions SR2:SR0 Source for Right Channel ADC 6 Mono Mix 7 PHONE input Default: 0000h RECORD GAIN REGISTER (1Ch) This register controls the input levels for both channels of the stereo ADC. The inputs come from the Record Select ...
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Register Descriptions support). VRA is indicated by a "1" in bit 0. The two MSBs, ID1 and ID0, show the current Codec Identity as defined by the Identity pins ID1#, ID0#. Note that the external logic connections to ID1#, ID0# ...
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Low Power Modes (Continued) Improving System Performance The audio codec is capable of dynamic range performance in excess of 90 db., but the user must pay careful attention to several factors to achieve this. A primary consideration is keeping analog ...
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Multiple Codecs (Continued) configured as ’Primary’ either by leaving ID1#, ID0# open (NC strapping them externally to DV ply). The difference between Primary and Secondary codec modes is in their timing source and in the Tag Bit handling ...
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Multiple Codecs (Continued) FIGURE 9. Multiple Codecs using Extended AC Link Test Modes AC ’97 Rev 2.1 defines two test modes: ATE test mode and Vendor test mode. Cold Reset is the only way to exit either of them. The ...
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