W682310RG Nuvoton Technology Corporation of America, W682310RG Datasheet
W682310RG
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W682310RG Summary of contents
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W682510/W682310 DUAL-CHANNEL VOICEBAND CODECS ADVANCED Publication Release Date: April 2005 - 1 - Revision A10 ...
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GENERAL DESCRIPTION The W682510 and W682310 are general-purpose dual channel PCM CODECs with pin-selectable μ- Law or A-Law companding. The device is compliant with the ITU G.712 specification. It operates from a single power supply (+5V for the W682510, ...
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BLOCK DIAGRAM PCMT1 PCMT1 PCMT2 PCMT2 PC FST FST M BCLK BCLK Int FSR FSR erf PCMMS PCMMS ac PCMR1 PCMR1 PCMR2 PCMR2 DATA T1 DATA T1 DATA R1 DATA R1 DATA T2 DATA T2 DATA R2 DATA R2 ...
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TABLE OF CONTENTS 1. GENERAL DESCRIPTION ................................................................................................................. 2 1. GENERAL DESCRIPTION ................................................................................................................. 2 2. FEATURES ......................................................................................................................................... 2 3. BLOCK DIAGRAM ............................................................................................................................. 3 4. TABLE OF CONTENTS...................................................................................................................... 4 5. PIN CONFIGURATION ....................................................................................................................... 6 6. PIN DESCRIPTION ............................................................................................................................. 7 7. FUNCTIONAL ...
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ELECTRICAL CHARACTERISTICS .............................................................................................. 20 10.1. General Parameters W682510 4.5V – 5.5V 10.2. General Parameters W682310 2.7V – 3.8V 10.3. Analog Signal Level and Gain Parameters 10.4. Analog Distortion and Noise Parameters 10.5. Analog Input and Output Amplifier Parameters 10.6. ...
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PIN CONFIGURATION V REF RO2 NC RO1 PUI PCMMS SSD FSR PCMR2 PCMR1 V REF RO2 RO2 RO1 RO1 PUI PUI PCMMS PCMMS SSD SSD FSR FSR PCMR2 PCMR2 ...
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PIN DESCRIPTION Pin # Pin # Pin Functionality Name SSOP SOP (CH1 = Channel 1, CH2 = Channel 2) PDIP This pin is used to bypass the signal ground. It needs to be decoupled to V ...
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FUNCTIONAL DESCRIPTION W682510/W682310 is a single-rail, dual channel PCM CODEC for voiceband applications. The CODEC complies with the specifications of the ITU-T G.712 recommendation. The CODEC includes two complete μ-Law and A-Law companders. The μ-Law and A-Law companders are ...
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Law format. The μ-Law or A-Law format is pin-selectable through the μ/A-Law pin. The compression format can be selected according to Table 7.1. TABLE 7.1: PIN-SELECTABLE COMPRESSION FORMAT μ/A-Law Pin V (HIGH (LOW) SSA The digital 8-bit μ-Law ...
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This device is compatible with the ITU-T coding law and output coding format recommendation. TABLE 7.15: PCM CODES FOR ZERO AND FULL SCALE Level Sign bit + ...
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PCMR1 The PCM signal input for channel 1 when in the parallel mode. D/A conversion is performed on the serial PCM signal input to this pin. The FSR signal, synchronous with the serial PCM signal, and the BCLK signal, ...
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V REF This pin carries the signal ground voltage level and requires a bypass capacitor. A 0.1μF ceramic (with low ESR for good high frequency response) capacitor needs to be connected between the V pin and the V pin. ...
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BCLK This is the shift clock signal input for the PCMR1, PCMR2, PCMT1, and PCMT2 signals. The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048 or 200 kHz. ...
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Power Down Mode When the power up indicator pin, PUI, is set LOW all internal circuits will go into the power down state. It will take milliseconds for the PLL to lock when operation is resumed ...
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TIMING DIAGRAMS BCLK FST PCMT1 MSB Channel 1 Transmit PCM Data Figure 8-1a. Transmit Side Serial Mode Timing (PCMMS=0) BCLK FSR PCMR2 MSB Channel 1 Receive PCM Data Figure 8-1b. Receive Side Serial ...
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BCLK FST FSR PCMT1 MSB PCMR2 Channel 1 PCM Data Figure 8-3a. Burst Mode with Serial Timing (PCMMS=0) BCLK FST FSR PCMTx MSB D6 ...
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TABLE 8.1: PCM SYNCHRONIZATION PARAMETERS SYMBOL DESCRIPTION f FST, FSR frequency FS t FST, FSR Pulse Width WS t FST, FSR allowable jitter j f BCLK frequency BCLK D BCLK Duty Cycle C t FSR, FST, BCLK, PCMR1, PCMR2, PUI, ...
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TABLE 8.2: PCM TIMING PARAMETERS SYMBOL DESCRIPTION t FST, FSR Pulse Width WS t BCLK low to FST high setup time XS t FST high to BCLK low hold time SX t PCMT1, PCMT2 output delay 100 pF ...
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ABSOLUTE MAXIMUM RATINGS TABLE 9.1: ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS) Condition Junction temperature Storage temperature range Voltage Applied to any pin Voltage applied to any pin (Input current limited to +/-20 mA) Lead temperature (soldering – 10 seconds) V ...
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ELECTRICAL CHARACTERISTICS 10. ENERAL ARAMETERS Symbol Parameters V Input Low Voltage IL V Input High Voltage IH V PCMT1, PCMT2 OL Low Voltage V Current (Operating ADC + DAC I V Current (Standby) ...
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Symbol Parameters I Input High Leakage Current IH I PCMT1, PCMT2 OL Leakage Current C Digital Input Capacitance IN C PCMT1, PCMT2 OUT Capacitance 1. Typical values 25° All min/max limits are guaranteed by Winbond via ...
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NALOG IGNAL =5V ±10%; V W682510 W682310: V =2.7V to 3.8V PARAMETER SYM. Reference Level L 0 dBm0 = +0.8 dBm @ ABS Out 600Ω load 1020 Hz W682510 5V Reference Level ...
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Gain Variation –40 dBm0 LT vs. Level Tone -40 to –50 dBm0 (1020 Hz -50 to –55 dBm0 relative to –10 dBm0) W682510/W682310 --- -0.3 +0.3 --- -0.5 +0.5 --- -1.2 +1.2 Publication Release Date: April 2005 ...
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A D NALOG ISTORTION AND =5V ±10%; V W682510 W682310: V =2.7V to 3.8V PARAMETER SYM. Total Distortion vs. D LTμ Level Tone (1020 Hz, μ-Law, C-Message Weighted) Total Distortion vs. D LTA Level Tone ...
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A I NALOG NPUT AND =5V ±10%; V W682510 W682310: V =2.7V to 3.8V PARAMETER AI1, AI2 Input Offset Voltage AI1, AI2 Input Resistance AO1-, AO2- Output Amplitude AO1-, AO2- Load Resistance AO1-, AO2- Load ...
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D I/O IGITAL TABLE 10.61: μ-LAW ENCODE DECODE CHARACTERISTICS Normalized Encode Decision D7 D6 Levels Sign Chord 8159 1 0 7903 : 4319 1 0 4063 : 2143 1 0 2015 : 1055 1 0 991 : 511 1 ...
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TABLE 10.62: A-LAW ENCODE DECODE CHARACTERISTICS Normalized Encode D7 D6 Decision Sign Chord Levels 4096 1 0 3968 : 2048 1 0 2048 : 1088 1 0 1024 : 544 1 0 512 : 272 1 0 256 : 136 ...
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TABLE 10.63: PCM CODES FOR ZERO AND FULL SCALE Level Sign bit Chord bits (D7) (D6,D5,D4) + Full Scale 1 + Zero 1 - Zero 0 - Full Scale 0 TABLE 10.64: PCM CODES FOR 0DBM0 OUTPUT Sample Sign bit ...
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TYPICAL APPLICATION CIRCUIT 0.1 μ F Channel 2 Analog Output Channel 1 Analog 1 μ F Output PCM 2 Ch Serial Input Frame Sync Input FIGURE 11.1: APPLICATION CIRCUIT FOR SERIAL MODE OPERATION V Power Up DD Input W682510/W2310 ...
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V Power Up DD Input μ 0.1 F Channel 2 Analog Output Channel 1 Analog Output μ PCM Ch2 Serial Input PCM Ch1 Serial Input Frame Sync Input FIGURE 11.2: APPLICATION CIRCUIT FOR PARALLEL MODE OPERATION W682510/W682310 W682510/W682310 ...
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PACKAGE DRAWING AND DIMENSIONS 12.1. 20L (PDIP) P LASTIC DIMENSION (MM) SYMBOL MIN 0. 3918 2 B 0. 0.20 ...
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SSOP – 209 S MIL SEATING Y e DIMENSION (MM) SYMBOL MIN 0.05 A2 1.65 b 0.22 c 0.09 D 6.90 E 5. 0.55 ...
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SOP – 300 MIL PLA N E DIMENSION (MM) SYMBOL MIN. A 2.35 A1 0.10 b 0.33 c 0.23 E 7.40 D 15. 10. ...
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ORDERING INFORMATION Product Number Descriptor Key W682510 _ Product Family W682510 Product When ordering W682510 series devices, please refer to the following part numbers. W682310 _ Product Family W682310 Product When ordering W682310 series devices, please refer to the ...
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VERSION HISTORY VERSION DATE PAGE 0.31 Mar 2003 All 0.34 Apr. 2003 0.35 May 2003 A10 April 2005 35 Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical ...