WAU8812YG Nuvoton Technology Corporation of America, WAU8812YG Datasheet - Page 9

• Manufacturer Part Number: WAU8812YG
• Description: IC MON AUD CODEC SPKR DVR 32-QFN
• Manufacturer: Nuvoton Technology Corporation of America
• Series: emPowerAudio™r
• Type: Audio Codecr

Specifications of WAU8812YG

• Data Interface: Serial
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 91 / 93
• Voltage - Supply, Analog: 2.5 V ~ 3.6 V
• Voltage - Supply, Digital: 1.71 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• For Use With: WAU8812EVB - BOARD EVALUATION FOR WAU8812
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

VDDC = 1.8V, VDDA = VDDB = SPK3V = 3.3V, T
otherwise stated.
Automatic Level Control (ALC)/Limiter – ADC only
Target Record Level
Programmable Gain
Programmable Gain Step
Size
Gain Hold Time
Gain Ramp-Up (Decay)
Time
Gain Ramp-Down (Attack)
Time
Digital Input / Output
Input HIGH Level
Input LOW Level
Output HIGH Level
Output LOW Level
Notes
emPowerAudio
Preliminary Datasheet Revision 0.85
1. Full Scale is relative to VDDA (FS = VDDA/3.3.) Input level to RIP and LIP is limited to a maximum of -3dB so
2. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full-scale output and the
3. THD+N (dB) - THD+N are a ratio, of the rms values, of (Noise + Distortion)/Signal.
4. Hold Time is the length of time between a signal detected being too quiet and beginning to ramp up the gain. It
5. Ramp-up and Ramp-Down times are defined as the time it takes to change the PGA gain by 6dB of its gain
6. All hold, ramp-up and ramp-down times scale proportionally with MCLK
7. The maximum output voltage can be limited by the speaker power supply. If MOUT3V or SPK3V is, set then
that THD+N performance will not be reduced.
output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).
does not apply to ramping down the gain when the signal is too loud, which happens without a delay.
range.
VDDSPK should be 1.5xVDDA to prevent clipping taking place in the output stage (when PGA gains are set to
0dB).
5, 6
5, 6
PARAMETER
™
4, 6
SYMBOL
tHOLD
tDCY
tATK
V
V
V
V
OH
OL
IH
IL
Guaranteed Monotonic
MCLK=12.288MHz
ALC Mode
Limiter Mode
ALC Mode
Limiter Mode
I
I
OL
OH
TEST CONDITIONS
ALCM=0
MCLK=12.288MHz
ALCM=1
MCLK=12.288MHz
ALCM=0
MCLK=12.288MHz
ALCM=1
MCLK=12.288MHz
= 1mA
= -1mA
Page 9 of 15
A
= +25
o
C, 1kHz signal, fs = 48kHz, 24-bit audio data unless
(time doubles with each step)
(time doubles with each step)
(time doubles with each step)
(time doubles with each step)
VDDC
VDDC
-28.5
0.7 ×
0.9 ×
0.73 / 1.45 / 2.91 / … / 744
0.83 / 1.66 / 3.33 / … / 852
0.18 / 0.36 / 0.73 / … / 186
MIN
3.3 / 6.6 / 13.1 / … / 3360
-12
0 / 2.67 / …/ 43691 (time
doubles with each step)
TYP
0.75
3.25
VDDC
VDDC
35.25
0.3 ×
MAX
0.1 x
October 2008
-6
UNIT
ms
ms
ms
ms
ms
dB
dB
dB
V
V
V
V