CS42518-DQZR Cirrus Logic Inc, CS42518-DQZR Datasheet - Page 54

• Manufacturer Part Number: CS42518-DQZR
• Description: IC CODEC S/PDIF RCVR 64-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42518-DQZR

• Package / Case: 64-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 8
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 114 / 110
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 8
• Conversion Rate: 192 KSPs
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 2 ADC, 8 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1502 - BOARD EVAL FOR CS42518 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

54
6.7.5
6.8
6.8.1
6.9
6.9.1
Digital Silence AES Format2 AES Format1 AES Format0
RATIO7(2
7
7
FORCE PLL LOCK (FRC_PLL_LK)
OMCK/PLL_CLK Ratio (address 07h) (Read Only)
OMCK/PLL_CLK RATIO (RATIOX)
RVCR Status (address 08h) (Read Only)
DIGITAL SILENCE DETECTION (DIGITAL SILENCE)
Default = 0
Function:
Default = xxxxxxxx
Function:
Default = x
0 - Digital Silence not detected
1 - Digital Silence detected
Function:
1
)
SW_CTRL1 SW_CTRL0 UNLOCK
unlocked when the FRC_PLL_LK bit is set to ‘1’b, RMCK will not equal OMCK.
This bit is used to enable the PLL to lock to the S/PDIF input stream or the SAI_LRCK with the ab-
sence of a clock signal on OMCK. When set to a ‘1’b, the auto-detect sample frequency feature will
be disabled and the SW_CTRLX bits must be set to ‘00’b. The OMCK/PLL_CLK Ratio (address 07h)
(Read Only) register contents are not valid, and the PLL_CLK[2:0] bits will be set to ‘111’b. Use the
DE-EMPH[1:0] bits to properly apply de-emphasis filtering.
This register allows the user to find the exact absolute frequency of the recovered MCLK coming from
the PLL. This value is represented as an integer (RATIO7:6) and a fractional (RATIO5:0) part. For
example, an OMCK/PLL_CLK ratio of 1.5 would be displayed as 60h.
The CS42518 will auto-detect a digital silence condition when 1548 consecutive zeros have been de-
tected.
RATIO6(2
0
0
1
1
6
6
0
)
RATIO5(2
0
1
0
1
5
5
-1
Table 12. Master Clock Source Select
)
RATIO4(2
X
X
0
1
0
1
4
4
Manual setting, MCLK sourced from PLL.
Manual setting, MCLK sourced from OMCK.
Hold, keep same MCLK source.Auto switch, MCLK
sourced from OMCK.
Auto switch, MCLK sourced from PLL.
Auto switch, MCLK sourced from OMCK.
-2
)
RATIO3(2
Active_CLK
3
3
-3
)
Description
RVCR_CLK2
RATIO2(2
2
2
-4
)
RVCR_CLK1
RATIO1(2
1
1
-5
)
CS42518
RVCR_CLK0
RATIO0(2
DS584F1
0
0
-6
)