CS42436-CMZ Cirrus Logic Inc, CS42436-CMZ Datasheet - Page 44
![IC CODEC 108DB 192KHZ 52-MQFP](/photos/6/80/68084/cs42436-cmz_sml.jpg)
CS42436-CMZ
Manufacturer Part Number
CS42436-CMZ
Description
IC CODEC 108DB 192KHZ 52-MQFP
Manufacturer
Cirrus Logic Inc
Type
Audio Codecr
Datasheet
1.CS42436-CMZ.pdf
(61 pages)
Specifications of CS42436-CMZ
Package / Case
52-MQFP, 52-PQFP
Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
6 / 6
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
105 / 108 (Differential), 102 / 105 (Single-Ended)
Voltage - Supply, Analog
3.14 V ~ 5.25 V
Voltage - Supply, Digital
3.14 V ~ 3.47 V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Number Of Adc Inputs
6
Number Of Dac Outputs
6
Conversion Rate
192 KSPS
Interface Type
Serial (I2C, SPI)
Resolution
24 bit
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 10 C
Number Of Channels
6 ADC/6 DAC
Thd Plus Noise
- 98 dB ADC / - 98 dB DAC, - 95 dB ADC / - 95 dB DAC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
598-1612
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44
7.6
7.6.1
7.6.2
7.6.3
7.6.4
ADC1-2_HPF
FREEZE
7
ADC Control & DAC De-Emphasis (Address 05h)
ADC1-2 High-Pass Filter Freeze (ADC1-2_HPF FREEZE)
Default = 0
Function:
When this bit is set, the internal high-pass filter will be disabled for ADC1 and ADC2.The current DC offset
value will be frozen and continue to be subtracted from the conversion result. See
Characteristics” on page
ADC3 High Pass Filter Freeze (ADC3_HPF FREEZE)
Default = 0
Function:
When this bit is set, the internal high-pass filter will be disabled for ADC3.The current DC offset value will
be frozen and continue to be subtracted from the conversion result. See
tics” on page
DAC De-Emphasis Control (DAC_DEM)
Default = 0
0 - No De-Emphasis
1 - De-Emphasis Enabled (Auto-Detect Fs)
Function:
Enables the digital filter to maintain the standard 15μs/50μs digital de-emphasis filter response at the
auto-detected sample rate of either 32, 44.1, or 48 kHz. De-emphasis will not be enabled, regardless of
this register setting, at any other sample rate.
ADC1 Single-Ended Mode (ADC1 SINGLE)
Default = 0
0 - Disabled; Differential input to ADC1
1 - Enabled; Single-Ended input to ADC1
Function:
When enabled, this bit allows the user to apply a single-ended input to the positive terminal of ADC1. A
+6 dB digital gain is automatically applied to the serial audio data of ADC1. The negative leg must be driv-
en to the common mode of the ADC. See
ADC3_HPF
FREEZE
6
16.
DAC_DEM
5
16.
SINGLE
ADC1
4
Figure 21 on page 50
SINGLE
ADC2
3
SINGLE
for a graphical description.
ADC3
2
“ADC Digital Filter Characteris-
AIN5_MUX
1
“ADC Digital Filter
CS42436
AIN6_MUX
DS647F2
0