CS42416-CQZ Cirrus Logic Inc, CS42416-CQZ Datasheet - Page 48
![IC CODEC 6CH 110DB 192KHZ 64LQFP](/photos/6/80/68054/cs42416-cqz_sml.jpg)
CS42416-CQZ
Manufacturer Part Number
CS42416-CQZ
Description
IC CODEC 6CH 110DB 192KHZ 64LQFP
Manufacturer
Cirrus Logic Inc
Type
General Purposer
Datasheet
1.CS42416-CQZ.pdf
(73 pages)
Specifications of CS42416-CQZ
Package / Case
64-LQFP
Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
2 / 6
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
114 / 110
Voltage - Supply, Analog
4.75 V ~ 5 V
Voltage - Supply, Digital
3.13 V ~ 5.25 V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Number Of Adc Inputs
2
Number Of Dac Outputs
6
Conversion Rate
192 KSPS
Interface Type
Serial (I2C, SPI)
Resolution
24 bit
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 10 C
Number Of Channels
2 ADC/6 DAC
Thd Plus Noise
- 100 dB ADC / - 100 dB DAC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
598-1028
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS42416-CQZ
Manufacturer:
TI
Quantity:
1 007
Company:
Part Number:
CS42416-CQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Company:
Part Number:
CS42416-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
48
6.7
6.7.1
6.7.2
6.7.3
RMCK_DIV1
7
Clock Control (address 06h)
RMCK DIVIDE (RMCK_DIVX)
OMCK FREQUENCY (OMCK FREQX)
PLL LOCK TO LRCK (PLL_LRCK)
Default = 00
Function:
Default = 00
Function:
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, the internal PLL of the CS42416 will lock to the ADC_LRCK of the ADC serial port
(ADC_LRCK) while the ADC_SP is in Slave Mode.
Divides/multiplies the internal MCLK, either from the PLL or OMCK, by the selected factor.
Sets the appropriate frequency for the supplied OMCK.
RMCK_DIV0
OMCK Freq1 OMCK Freq0
6
0
0
1
1
OMCK Freq1
RMCK_DIV1 RMCK_DIV0
5
0
0
1
1
Table 10. OMCK Frequency Settings
0
1
0
1
Table 9. RMCK Divider Settings
OMCK Freq0
11.2896 MHz or 12.2880 MHz
16.9344 MHz or 18.4320 MHz
22.5792 MHz or 24.5760 MHz
Reserved
4
0
1
0
1
PLL_LRCK
Description
Multiply by 2
Divide by 1
Divide by 2
Divide by 4
3
Description
SW_CTRL1
2
SW_CTRL0
1
FRC_PLL_LK
CS42416
DS602F1
0