CS42L55-CNZ Cirrus Logic Inc, CS42L55-CNZ Datasheet - Page 45

• Manufacturer Part Number: CS42L55-CNZ
• Description: IC CODEC STER H-HDPN AMP 36QFN
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS42L55-CNZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 95 / 99
• Voltage - Supply, Analog: 1.65 V ~ 2.71 V
• Voltage - Supply, Digital: 1.65 V ~ 2.71 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-QFN
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 3
• No. Of Output Channels: 3
• Adc / Dac Resolution: 24bit
• Sampling Rate: 48kSPS
• Ic Interface Type: I2C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1506 - BOARD EVAL FOR CS42L55 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1629

DS773F1
6.5.2
6.5.3
6.6
6.6.1
6.7
6.7.1
Reserved
DIGMUX
7
7
Class H Power Control (Address 06h)
Miscellaneous Control (Address 07h)
32 kHz Sample Rate Group
Specifies whether or not the input/output sample rate is 8 kHz, 16 kHz or 32 kHz.
Internal MCLK/LRCK Ratio
Configures the internal MCLK/LRCK ratio.
Adaptive Power Adjustment
Configures how the power to the headphone and line amplifiers adapts to the output signal level.
Digital MUX
Selects the signal source for the ADC serial port.
32kGROUP
0
1
Application:
RATIO[1:0]
00
01
10
11
Application:
ADPTPWR[1:0]
00
01
10
11
Application:
DIGMUX
0
1
Reserved
Reserved
6
6
8 kHz, 16 kHz or 32 kHz sample rate?
No
Yes
“Serial Port Clocking” on page 34
Internal MCLK Cycles per LRCK
Reserved
125
Reserved
136
“Serial Port Clocking” on page 34
Power Supply
Adapted to volume setting; Voltage level is determined by the sum of the relevant volume settings
Fixed - Headphone and Line Amp supply = +/-VCP/2
Fixed - Headphone and Line Amp supply = +/-VCP
Adapted to Signal; Voltage level is dynamically determined by the output signal
“Class H Amplifier” on page 27
SDOUT Signal Source
ADC
DSP Mix
ADPTPWR1
Reserved
5
5
ADPTPWR0
Reserved
4
4
Reserved
ANLGZC
3
3
Reserved
DIGSFT
2
2
Reserved
Reserved
1
1
CS42L55
Reserved
FREEZE
0
0
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