PLDC20G10-25PC Cypress Semiconductor Corp, PLDC20G10-25PC Datasheet - Page 6

• Manufacturer Part Number: PLDC20G10-25PC
• Description: IC SPLD 10MACROCELL 25NS 24-DIP
• Manufacturer: Cypress Semiconductor Corp

Specifications of PLDC20G10-25PC

• Programmable Type: SPLD
• Number Of Macrocells: 10
• Voltage - Input: 5V
• Speed: 25ns
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• Family Name: PLDC20G10
• Process Technology: CMOS
• # Macrocells: 10
• # I/os (max): 10
• Propagation Delay Time: 25ns
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: 0C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 24
• Supply Current: 55mA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1284

Document #: 38-03010 Rev. *A
AC Test Loads and Waveforms (Commercial)
Switching Characteristics
Switching Characteristics
Equivalent to: THÉVENIN EQUIVALENT (Commercial)
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
Notes:
10. t
11. f
PD
EA
ER
PZX
PXZ
CO
S
H
P
WH
WL
MAX
Parameter
PD
EA
ER
PZX
PXZ
CO
S
H
Parameter
8. Part (a) of AC Test Loads and Waveforms used for all parameters except t
9. The parameters t
[10]
0.5V for an enabled LOW input.
registered data path operation (no feedback) can be calculated as the greater of (t
guaranteed f
P
MAX
, minimum guaranteed clock period is that guaranteed for state machine operation and is calculated from t
[11]
, minimum guaranteed operating frequency, is that guaranteed for state machine operation and is calculated from f
OUTPUT
MAX
OUTPUT
Input or Feedback to Non-Registered Output
Input to Output Enable
Input to Output Disable
Pin 11 to Output Enable
Pin 11 to Output Disable
Clock to Output
Input or Feedback Set-Up Time
Hold Time
Input or Feedback to Non-Registered Output
Input to Output Enable
Input to Output Disable
Pin 11 to Output Enable
Pin 11 to Output Disable
Clock to Output
Input or Feedback Set-up Time
Hold Time
Clock Period
Clock High Time
Clock Low Time
Maximum Frequency
ER
for registered data path operation (no feedback) can be calculated as the lower of 1/(t
INCLUDING
JIG AND
SCOPE
and t
5V
PXZ
99Ω
are measured as the delay from the input disable logic threshold transition to V
R1 238 Ω
(319Ω MIL)
Description
Description
50pF
Over Operating Range
Over Operating Range
(a)
2.08V=V
USE ULTRA37000™ FOR
thc
R2 170Ω
(236Ω MIL)
ALL NEW DESIGNS
[3, 8, 9]
[3, 8, 9]
ER
, t
OUTPUT
PZX
Min. Max. Min. Max. Min. Max. Min. Max.
15
Min. Max. Min. Max. Min. Max. Min. Max.
45.4
0
, and t
12
22
INCLUDING
JIG AND
SCOPE
0
8
8
B–20
WH
B–15
5V
Equivalent to: THÉVENIN EQUIVALENT (Military/Industrial)
PXZ
+ t
20
20
20
17
17
15
WL
15
15
15
12
12
10
. Part (b) of AC Test Loads and Waveforms used for t
) or (t
OUTPUT
S
18
41.6
0
12
24
10
10
+ t
0
R1 238Ω
(319Ω MIL)
B–25
Military/Industrial
H
B–20
(b)
).
5 pF
WH
Commercial
25
25
25
20
20
15
+ t
20
20
20
15
15
12
P
OH
WL
= t
) or 1/(t
– 0.5V for an enabled HIGH output or V
S
136 Ω
+ t
33.3
20
0
R2 170Ω
(236Ω MIL)
15
30
12
12
CO
0
–30
MAX
S
. The minimum guaranteed period for
–25
+ t
H
= 1/(t
30
30
30
25
25
20
).
25
25
25
20
20
15
PLDC20G10B
S
2.13V=V
+ t
PLDC20G10
18.1
35
CO
0
30
55
17
17
0
). The minimum
–40
–35
ER
thm
Page 6 of 14
40
40
40
25
25
25
35
35
35
25
25
25
, t
PZX
, and t
Unit
MHz
Unit
OL
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PXZ
+
.
[+] Feedback