PALCE16V8-7JC Cypress Semiconductor Corp, PALCE16V8-7JC Datasheet - Page 2
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PALCE16V8-7JC
Manufacturer Part Number
PALCE16V8-7JC
Description
IC SPLD 8 MACROCELL 15NS 20-PLCC
Manufacturer
Cypress Semiconductor Corp
Specifications of PALCE16V8-7JC
Programmable Type
PAL FLASH
Number Of Macrocells
8
Voltage - Input
5V
Speed
15ns
Mounting Type
Surface Mount
Package / Case
20-PLCC
Family Name
Pal®
Process Technology
EECMOS
# Macrocells
8
# I/os (max)
8
Frequency (max)
125MHz
Propagation Delay Time
7.5ns
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
20
Supply Current
115mA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1279
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PALCE16V8-7JC
Manufacturer:
CYP
Quantity:
5 510
Company:
Part Number:
PALCE16V8-7JC
Manufacturer:
NSC
Quantity:
5 510
Selection Guide
Functional Description
The PALCE16V8 is executed in a 20-pin 300-mil molded DIP,
a 300-mil cerdip, a 20-lead square ceramic leadless chip car-
rier, and a 20-lead square plastic leaded chip carrier.
The device provides up to 16 inputs and 8 outputs. The
PALCE16V8 can be electrically erased and reprogrammed.
The programmable macrocell enables the device to function
as a superset to the familiar 20-pin PLDs such as 16L8, 16R8,
16R6, and 16R4.
The PALCE16V8 features 8 product terms per output and 32
input terms into the AND array. The first product term in a mac-
rocell can be used either as an internal output enable control
or as a data product term.
There are a total of 18 architecture bits in the PALCE16V8
macrocell; two are global bits that apply to all macrocells and
16 that apply locally, two bits per macrocell. The architecture
bits determine whether the macrocell functions as a register or
combinatorial with inverting or noninverting output. The output
enable control can come from an external pin or internally from
a product term. The output can also be permanently enabled,
functioning as a dedicated output or permanently disabled,
functioning as a dedicated input. Feedback paths are select-
able from either the input/output pin associated with the mac-
rocell, the input/output pin associated with an adjacent pin, or
from the macrocell register itself.
Configuration Table
Document #: 38-03025 Rev. **
PALCE16V8-5
PALCE16V8-7
PALCE16V8-10
PALCE16V8-15
PALCE16V8-25
PALCE16V8L-15
PALCE16V8L-25
Shaded area contains preliminary information.
Generic Part Number
CG
0
0
1
1
1
0
CG
1
1
0
0
1
1
CL0
0
1
0
1
1
Com’l/Ind
(continued)
x
7.5
10
15
25
15
25
5
Registered Output
Combinatorial I/O
Combinatorial Output
Input
Combinatorial I/O
t
PD
ns
Mil
10
15
25
15
25
Cell Configuration
Com’l/Ind
10
12
15
12
15
3
7
t
S
ns
Power-Up Reset
All registers in the PALCE16V8 power-up to a logic LOW for
predictable system initialization. For each register, the associ-
ated output pin will be HIGH due to active-LOW outputs.
Electronic Signature
An electronic signature word is provided in the PALCE16V8
that consists of 64 bits of programmable memory that can con-
tain user-defined data.
Security Bit
A security bit is provided that defeats the readback of the in-
ternal programmed pattern when the bit is programmed.
Low Power
The Cypress PALCE16V8 provides low-power operation
through the use of CMOS technology, and increased testability
with Flash reprogrammability.
Product Term Disable
Product Term Disable (PTD) fuses are included for each prod-
uct term. The PTD fuses allow each product term to be individ-
ually disabled.
Mil
10
12
20
12
20
Com’l/Ind
Registered Med PALs
Registered Med PALs
Small PALs
Small PALs
16L8 only
10
12
10
12
4
5
7
t
CO
ns
Devices Emulated
Mil
10
10
12
12
20
Com’l
115
115
PALCE16V8
90
90
90
55
55
I
CC
Page 2 of 13
mA
Mil/Ind
130
130
130
65
65