PALC22V10L-25PC Cypress Semiconductor Corp, PALC22V10L-25PC Datasheet - Page 2
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PALC22V10L-25PC
Manufacturer Part Number
PALC22V10L-25PC
Description
IC SPLD 10MACROCELL 25NS 24-DIP
Manufacturer
Cypress Semiconductor Corp
Specifications of PALC22V10L-25PC
Programmable Type
PAL FLASH
Number Of Macrocells
10
Voltage - Input
5V
Speed
25ns
Mounting Type
Through Hole
Package / Case
24-DIP (0.300", 7.62mm)
Family Name
Pal®
Process Technology
CMOS
# Macrocells
10
# I/os (max)
10
Frequency (max)
41.6MHz
Propagation Delay Time
25ns
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
0C to 75C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
24
Supply Current
55mA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1275
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PALC22V10L-25PC
Manufacturer:
CY
Quantity:
6 229
Part Number:
PALC22V10L-25PC
Manufacturer:
CYP
Quantity:
20 000
Selection Guide
Functional Description
The PALCE22V10 is executed in a 24-pin 300-mil molded DIP,
a 300-mil cerDIP, a 28-lead square ceramic leadless chip car-
rier, a 28-lead square plastic leaded chip carrier, and provides
up to 22 inputs and 10 outputs. The PALCE22V10 can be elec-
trically erased and reprogrammed. The programmable macro-
cell provides the capability of defining the architecture of each
output individually. Each of the 10 potential outputs may be
specified as “registered” or “combinatorial.” Polarity of each
output may also be individually selected, allowing complete
flexibility of output configuration. Further configurability is pro-
vided through “array” configurable “output enable” for each po-
tential output. This feature allows the 10 outputs to be recon-
figured as inputs on an individual basis, or alternately used as
a combination I/O controlled by the programmable array.
PALCE22V10 features a variable product term architecture.
There are 5 pairs of product term sums beginning at 8 product
terms per output and incrementing by 2 to 16 product terms
per output. By providing this variable structure, the PALCE
22V10 is optimized to the configurations found in a majority of
applications without creating devices that burden the product
term structures with unusable product terms and lower perfor-
mance.
Additional features of the Cypress PALCE22V10 include a
synchronous preset and an asynchronous reset product term.
These product terms are common to all macrocells, eliminat-
ing the need to dedicate standard product terms for initializa-
tion functions. The device automatically resets upon pow-
er-up.
The PALCE22V10, featuring programmable macrocells and
variable product terms, provides a device with the flexibility to
implement logic functions in the 500- to 800-gate-array com-
plexity. Since each of the 10 output pins may be individually
configured as inputs on a temporary or permanent basis, func-
Document #: 38-03027 Rev. **
PALCE22V10-5
PALCE22V10-7
PALCE22V10-10
PALCE22V10-15
PALCE22V10-25
Generic Part Number
(continued)
Com’l
7.5
10
15
25
5
t
PD
ns
Mil/Ind
10
15
25
Com’l
10
15
tions requiring up to 21 inputs and only a single output and
down to 12 inputs and 10 outputs are possible. The 10 poten-
tial outputs are enabled using product terms. Any output pin
may be permanently selected as an output or arbitrarily en-
abled as an output and an input through the selective use of
individual product terms associated with each output. Each of
these outputs is achieved through an individual programmable
macrocell. These macrocells are programmable to provide a
combinatorial or registered inverting or non-inverting output. In
a registered mode of operation, the output of the register is fed
back into the array, providing current status information to the
array. This information is available for establishing the next
result in applications such as control state machines. In a com-
binatorial configuration, the combinatorial output or, if the out-
put is disabled, the signal present on the I/O pin is made avail-
able to the array. The flexibility provided by both
programmable product term control of the outputs and variable
product terms allows a significant gain in functional density
through the use of programmable logic.
Along with this increase in functional density, the Cypress
PALCE22V10 provides lower-power operation through the use
of CMOS technology, and increased testability with Flash re-
programmability.
Configuration Table
3
5
6
t
C
S
0
0
1
1
1
ns
Mil/Ind
10
15
6
C
0
1
0
1
0
Registered/Combinatorial
Com’l
15
4
5
7
8
t
CO
Combinatorial/Active HIGH
Combinatorial/Active LOW
Registered/Active HIGH
Registered/Active LOW
ns
Mil/Ind
15
Configuration
7
8
PALCE22V10
Com’l
130
130
90
90
90
I
CC
Page 2 of 13
mA
Mil/Ind
150
120
120