ATF22LV10C-15SI Atmel, ATF22LV10C-15SI Datasheet - Page 6

• Manufacturer Part Number: ATF22LV10C-15SI
• Description: IC PLD EE 15NS 24-SOIC
• Manufacturer: Atmel

Specifications of ATF22LV10C-15SI

• Programmable Type: EE PLD
• Number Of Macrocells: 10
• Voltage - Input: 3.3V
• Speed: 15ns
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATF22LV10C15SI

3.7
3.8
4.
5.
6.
7.
6
Power-up Reset
The registers in the Atmel
V
buffer.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the
uncertainty of how V
Preload of Register Outputs
The ATF22LV10C registers are provided with circuitry to allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC
file preload sequence will be done automatically by most of the approved programmers after the programming.
Electronic Signature Word
There are 64-bits of programmable memory that are always available to the user, even if the device is secured.
These bits can be used for user-specific data.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF22LV10C fuse patterns. Once programmed,
fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible.
The security fuse should be programmed last, as its effect is immediate.
Programming/Erasing
Programming/erasing is performed using standard PLD programmers. See CMOS PLD Programming Hardware &
Software Support for information on software/programming.
Table 6-1.
Input and I/O Pin-keeper
All ATF22V10C family members have internal input and I/O pin-keeper circuits. Therefore, whenever inputs or
I/Os are not being driven externally, they will maintain their last driven state. This ensures that all logic array inputs
and device outputs are at known states. These are relatively weak active circuits that can be easily overridden by
TTL-compatible drivers (see Input and I/O diagrams on
Parameter
T
V
CC
1. The V
2. The clock must remain stable during T
3. After T
Atmel ATF22LV10C
PR
RST
crossing V
CC
PR
rise must be monotonic and start below 0.7V
Programming/Erasing
, all input and feedback setup times must be met before driving the clock pin high
RST
, all registers will be reset to the low state. The output state will depend on the polarity of the
CC
Description
Power-up Reset Time
Power-up Reset Voltage
actually rises in the system, the following conditions are required:
®
ATF22LV10C are designed to reset during power-up. At a point delayed slightly from
PR
page
7).
Typ
600
2.5
1,000
Max
3.0
0780M–PLD–7/10
Units
ns
V