MMA8205EG Freescale Semiconductor, MMA8205EG Datasheet - Page 42

• Manufacturer Part Number: MMA8205EG
• Description: Board Mount Accelerometers X- AXIS 50G SOIC 16
• Manufacturer: Freescale Semiconductor
• Series: MMA82r

Specifications of MMA8205EG

• Sensing Axis: X
• Acceleration: 50 g
• Sensitivity: 8.02 mV/g
• Package / Case: SOIC-16
• Axis: X or Y
• Acceleration Range: ±50g
• Voltage - Supply: 6.3 V ~ 30 V
• Output Type: Digital
• Bandwidth: -
• Interface: SPI
• Mounting Type: Surface Mount
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

A.3
The ten customer-programmed OTP locations (DEVCFG0, DEVCFG1 and REG-8 through REG-F) may be programmed when
the device is in test mode if the following sequence of operations is performed. Register access operations required for OTP pro-
gramming are described in
Bits which are unprogrammed may be programmed to a logic ‘1’ state. The device may be incrementally programmed if desired,
however once a bit is programmed to a logic ‘1’ state, it may not be reset to logic ‘0’ in the OTP array. Once the LOCK2 bit has
been set, no further changes to the OTP array are possible. Setting LOCK2 also enables parity detection when the device oper-
ates in normal mode.
A.4
Using the DIN /VGND, CLK, and DOUT pins, each address location of MMA81XXEG/MMA82XXEG/MMA82XXTEG can be read
and written from an external SPI interface shown in
MMA81XXEG
42
•
•
•
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Delay a minimum of 32 μs to allow the programming sequence to begin.
11. Read data value from address $29 until bit 5 is set.
12. If bit 4 of value read from address $29 is set, the programming operation did not complete successfully.
Program the OTP memory
Read the OTP memory
Access various internal signals of the MMA81XXEG/MMA82XXEG/MMA82XXTEG in Test mode
OTP PROGRAMMING OPERATIONS
Apply V
Apply V
Write the desired data values to the two registers via the SPI.
Transfer the data value $AA to device register address $30 via the SPI.
Transfer the data value $55 to device register address $30 via the SPI.
Transfer the data value $C6 to device register address $30 via the SPI.
Write the data value $00 to address $20 via the SPI. This will enable write access to the fuse mirror registers.
Write register data to be programmed into fuse array.
Write the data value $05 to address $20 via the SPI. The automatic programming sequence is initiated by this write
operation.
INTERNAL REGISTER ACCESS
D
HCAP
TEST
IN
/V
D
CLK
to the V
GND
to the H
OUT
Appendix
PP
CAP
/TEST pin.
pin. This may be accomplished through BUSIN if desired.
A.4.
PERIPHERAL
INTERFACE
Figure A-2. OTP Interface Overview
SERIAL
Figure A-2.
The corresponding registers may be used to:
REGISTER
ARRAY
ARRAY
OTP
TO DIGITAL
INTERFACE
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