MMA8104EG Freescale Semiconductor, MMA8104EG Datasheet - Page 24

• Manufacturer Part Number: MMA8104EG
• Description: Board Mount Accelerometers SOURCE ONLY
• Manufacturer: Freescale Semiconductor
• Series: MMA81r

Specifications of MMA8104EG

• Sensing Axis: Z
• Acceleration: 40 g
• Sensitivity: 10 mV/g
• Package / Case: SOIC-16 Wide
• Axis: Z
• Acceleration Range: ±40g
• Voltage - Supply: 6.3 V ~ 30 V
• Output Type: Digital
• Bandwidth: -
• Interface: SPI
• Mounting Type: Surface Mount
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.6.3
The Read/Write NVM command must be transmitted as a DSI long command structure. No action is taken by MMA81XXEG/
MMA82XXEG/MMA82XXTEG if this command is sent to the DSI Global Device Address.
There is no response if the Read/Write NVM Command is received within a DSI short command structure.
OTP data are accessed by fields, where a field is a combination of register address (RA3 - RA0) and bank select (B1, B0) bits.
Bank select bits are assigned during an Initialization or Reverse Initialization command. Individual bits with predefined functions
(the upper four bits of DEVCFG2) each have their own field address. The remaining OTP data are grouped into four-bit fields.
Field addresses are shown in
The structure of the OTP array results in data being programmed in 16-bit groups. DEVCFG1 and DEVCFG2 are in the same
group. As a result, a non-zero device address assigned during Initialization or Reverse Initialization will be permanently
programmed into the OTP array when any field within the two device configuration bytes is programmed.
To avoid programming a non-zero device address, ensure that device address 0 is assigned during Initialization or Reverse
Initialization before programming any other bit(s) in DEVCFG1 or DEVCFG2.
OTP programming operations occur when the Read/Write NVM command is executed after the NV bit has been set during a
preceding Initialization or Reverse Initialization command.
The minimum DSI Bus idle voltage must exceed 14 V when programming the OTP array.
When this command is executed while the NV bit is cleared, the DSI device address will be returned regardless of the state of
the register address and bank select bits. The Read Register Data command (described in
the full range of customer accessible data.
MMA81XXEG
24
RA3
D15
D15
D7
A3
A3
RA2
D14
D14
D6
A2
A2
Read/Write NVM Command
RA1
D13
D13
D5
A1
A1
RA0
D12
D12
D4
Table 4-13 Long Response Structure - Read/Write NVM Command (NV = 1)
Table 4-14 Long Response Structure - Read/Write NVM Command (NV = 0)
A0
A0
Data
RD3
D11
RA3
D11
Table
D3
0
4-15.
RD2
RA2
D10
D10
Table 4-12 Read Write NVM Command Structure
D2
0
RD1
RA1
D1
D9
D9
0
RD0
RA0
D0
D8
D8
0
Data
Data
A3
A3
D7
D7
1
1
A2
D6
D6
A2
1
1
Address
A1
A1
D5
B1
D5
1
A0
D4
B0
D4
A0
1
RD3
D3
C3
D3
A3
1
Section
RD2
Command
C2
D2
D2
A2
0
4.6.5) may be used to access
RD1
Freescale Semiconductor
D1
C1
D1
A1
0
RD0
D0
C0
D0
A0
1
0 to 8 bits
0 to 8 bits
0 to 8 bits
CRC
CRC
CRC
Sensors