MMA8205EGR2 Freescale Semiconductor, MMA8205EGR2 Datasheet - Page 17

• Manufacturer Part Number: MMA8205EGR2
• Description: Board Mount Accelerometers X- AXIS 50G SOIC 16
• Manufacturer: Freescale Semiconductor
• Series: MMA82r

Specifications of MMA8205EGR2

• Sensing Axis: X
• Acceleration: 50 g
• Sensitivity: 8.02 mV/g
• Package / Case: SOIC-16
• Axis: X or Y
• Acceleration Range: ±50g
• Voltage - Supply: 6.3 V ~ 30 V
• Output Type: Digital
• Bandwidth: -
• Interface: SPI
• Mounting Type: Surface Mount
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Sensors
Freescale Semiconductor
4.5
Detailed descriptions of command formats and responses are provided in this section.
4.5.1
The following abbreviations are used in the descriptions of DSI commands and responses.
4.5.1.1
DSI device address. This address will be set to the pre-programmed device address following reset, or zero if no pre-programmed
address has been assigned. If zero, the device address may be assigned during initialization or reverse initialization.
4.5.1.2
Ten-bit acceleration result produced by the device. This value is returned by the Read Acceleration Data command, described in
Section
4.5.1.3
These bits indicate the contents of DEVCFG1 bits 1 and 0 in response to a Request Status, Activate Self-Test Stimulus or Disable
Self-Test Stimulus command.
4.5.1.4
These bits are assigned during initialization or reverse initialization to select specific fields within the customer accessible data
registers. Bank selection affects Read/Write NVM command operation. Invalid combinations of B1 and B0 result in no response
from the device to the associated initialization or reverse initialization command.
Refer to
4.5.1.5
This bit indicates the success or failure of the bus test which is performed as part of an Initialization or Reverse Initialization com-
mand.
1 - Bus fault detected
0 - Bus test passed
4.5.1.6
This bit controls the state of the bus switch during an Initialization or Reverse Initialization command. It also indicates the state
of the bus switch in response to the Initialization, Request Status, Disable Self-Test Stimulus, Activate Self-Test Stimulus and
Reverse Initialization commands.
1 - Close bus switch, or bus switch closed
0 - Leave bus switch open, or bus switch opened
4.5.1.7
This three-bit field selects one of eight format control registers. Format control registers are described in
4.5.1.8
Contents of a format control register. This is the data to be written to the register by a Format Control command, or the contents
read from the register in response to a Format Control command.
4.5.4.
Section 4.6.3
DSI COMMAND DETAIL
DSI Device Address - (A3 - A0)
Acceleration Data - (AD9 - AD0)
Attribute Code Bits (AT1, AT0)
Bank Select (B1, B0)
Bus Fault Bit (BF)
Bus Switch Control/Status Bit (BS)
Format Control Register Address (FA2 - FA0)
Format Register Data (FD3 - FD0)
DSI COMMAND AND RESPONSE BIT DESCRIPTIONS
for further details regarding register programming and bank selection.
LOCK2
0
1
DEVGFG1[1]
Table 4-4 Attribute Code Bit Assignments
X
0
0
1
1
DEVGFG1[0]
X
0
1
0
1
AT1
1
0
0
1
1
AT0
0
0
1
0
1
Section
4.6.4.3.
MMA81XXEG
17