NHPXA270C5C416 Intel, NHPXA270C5C416 Datasheet - Page 101

• Manufacturer Part Number: NHPXA270C5C416
• Description: IC MPU 32BIT 416MHZ 356-PBGA
• Manufacturer: Intel

Specifications of NHPXA270C5C416

• Processor Type: XScale®
• Speed: 416MHz
• Voltage: 1.35V
• Mounting Type: Surface Mount
• Package / Case: 356-PBGA
• For Use With: 460-3472 - KIT DEV ZOOM STARTER FOR PXA270
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 868460

6.4.6.1
Electrical, Mechanical, and Thermal Specification
Symbols
tvlioAS
tvlioAH
tvlioASRW0
tvlioASRWn
tvlioCES
tvlioCEH
tvlioDSWH
tvlioDH
tvlioDSOH
tvlioDOH
tvlioRDYH
tvlioRWA
tvlioRWD
tvlioCD
NOTES:
1. Numbers shown as integer multiples of the CLK_MEM period are ideal. Actual numbers vary with pin-to-pin differences in
2. Maximum values reflect the register dynamic ranges.
3. Depending on the programmed value of MSC[RDN] and the clk_mem speed, this can be a significant amount of time.
loading and transition direction (rise or fall).
Processor does not drive the data bus during this time between transfers. If the VLIO does not drive the data bus during this
time between transfers, the data bus is not driven for this period of time. If MSC[RDN] is programmed to 60 (which equals 60
CLK_MEM cycles), then the data bus could potentially not be driven for 30*2 = 60 CLK_MEM cycles.
Table 6-20. VLIO Timing
Variable Latency I/O Read Timing
Figure 6-24
lists the timing parameters used in these diagrams.
Parameters
Address setup to nCS asserted
Address hold from nPWE/nOE de-
asserted
Address setup to nPWE/nOE
asserted (1st access)
Address setup to nPWE/nOE
asserted (next access(es))
nCS setup to nPWE/nOE asserted
nCS hold from nPWE/nOE de-
asserted
MD/DQM setup (minimum) to nPWE
de-asserted
MD/DQM hold from nPWE de-
asserted
MD setup to address changing
MD hold from address changing
RDY hold from nPWE/nOE de-
asserted
nPWE/nOE assert period between
writes
nPWE/nOE de-asserted period
between writes
nCS de-asserted after a read/write to
next nCS or nSDCS asserted
(minimum)
shows the timing for 32-bit variable-latency I/O (VLIO) memory reads.
MIN
1.5
1
2
3
2
2
1
5
1
0
0
4
4
1
MSCx[RRR]*2 +
MSC[RDF]+1 +
MSCx[RDF]+2
MSCx[RDN*2]
MSCx[RDN]
MSCx[RDN]
Waits
TYP
—
—
—
—
—
—
1
AC Timing Specifications
Intel® PXA270 Processor
MAX
Waits
31 +
30
30
32
60
15
—
—
—
1
3
2
1
1
2
clk_mem
clk_mem
clk_mem
clk_mem
clk_mem
clk_mem
clk_mem
clk_mem
clk_mem
clk_mem
clk_mem
clk_mem
Units
ns
ns
Table 6-20
1
Notes
6-37
—
—
—
—
—
—
—
—
—
—
—
—
—
3