PRIXP425BD Intel, PRIXP425BD Datasheet - Page 21

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PRIXP425BD

Manufacturer Part Number
PRIXP425BD
Description
IC NETWRK PROCESSR 533MHZ 492BGA
Manufacturer
Intel
Datasheets

Specifications of PRIXP425BD

Processor Type
Network
Features
XScale Core
Speed
533MHz
Voltage
1.3V
Mounting Type
Surface Mount
Package / Case
492-BGA
Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
866108

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PRIXP425BD
Manufacturer:
INTEL
Quantity:
528
Part Number:
PRIXP425BD
Manufacturer:
INTEL
Quantity:
364
Status:
12.
Problem:
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
No
The Intel
Some SDRAM Devices (SCR 2411)
Although the Intel
JEDEC SDRAM specification, some SDRAM manufacturers are shifting their devices’ implemen-
tation of an optional section of the specification, to maintain consistency between SDRAM
Single-Data-Rate (SDR) Memory and SDRAM Double-Data-Rate (DDR) Memory. That results in
an issue involving the Mode Register Set command.
In order to support vendor-specific, extended modes, the SDRAM must receive the Mode Register
Set command with the Bank Address (BA) bits set to a particular value. For normal operation, the
BA bits must be set to logic 00, during the Mode Register Set command.
The Intel
during the Mode Register Set Command. The JEDEC SDRAM specification states that the BA
values must be put to a valid state during the Mode Register Set command. However, the DDR
options to this specification require that the BA bits be set to support extended modes.
Memory known to work
Additional information may be added to this list as more data is collected.
Memory known to fail
1. Read LSR and check for errors.
2. Disable Receiver Time-out Interrupt Enable (RTOIE) via Interrupt Enable Register (IER) bit 4.
3. Read Data from FIFO.
4. Software Delay.
5. Read LSR, check for errors, and LOOP back to (3) if DR bit in LSR is SET.
6. No more data in FIFO: Re-enable RTOIE interrupt via IER bit 4.
7. DONE.
Fix.
Micron*
Winbond*
Elpida*
Winbond — W987Z6CB
— MT48LC8M16A2
— MT48LC16M16A2
— MT48LC32M16A2
— W981216BH
— W982516BH
— UPD45128163
— HM5225165B
— HM5259165B
— HM5257165B
®
®
IXP42X product line and IXC1100 control plane processors sets these bits to logic 11,
IXP425 A-0 Step Processor May Have Problems Working With
®
IXP42X product line and IXC1100 control plane processors comply with the
Non-Core Errata
21

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