MPC7410RX500LE Freescale Semiconductor, MPC7410RX500LE Datasheet - Page 18

• Manufacturer Part Number: MPC7410RX500LE
• Description: IC MPU 32BIT 500MHZ PPC 360-CBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC7410RX500LE

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 500MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 360-FCCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Electrical and Thermal Characteristics
4.2.3
The L2CLK frequency is programmed by the L2 Configuration Register (L2CR[4:6]) core-to-L2 divisor ratio. See
Table 14
output AC timing specifications as defined in
The L2SYNC_OUT signal is intended to be routed halfway out to the SRAMs and then returned to the L2SYNC_IN
input of the MPC7410 to synchronize L2CLK_OUT at the SRAM with the processor’s internal clock. L2CLK_OUT
at the SRAM can be offset forward or backward in time by shortening or lengthening the routing of L2SYNC_OUT
to L2SYNC_IN. See Freescale Application Note AN1794, Backside L2 Timing Analysis for the PCB Design
Engineer.
The minimum L2CLK frequency in
DLL introduces up to a full clock period delay in the L2CLK_OUTA, L2CLK_OUTB, and L2SYNC_OUT signals
so that the returning L2SYNC_IN signal is phase-aligned with the next core clock (divided by the L2 divisor ratio).
Do not choose a core-to-L2 divisor that results in an L2 frequency below this minimum, or the L2CLK_OUT signals
provided for SRAM clocking will not be phase-aligned with the MPC7410 core clock at the SRAMs.
The maximum L2CLK frequency shown in
designs will be able to operate in this mode. Most designs will select a greater core-to-L2 divisor to provide a longer
L2CLK period for read and write access to the L2 SRAMs. The maximum L2CLK frequency for any application of
the MPC7410 will be a function of the AC timings of the MPC7410, the AC timings for the SRAM, bus loading,
and printed-circuit board trace length.
Freescale is similarly limited by system constraints and cannot perform tests of the L2 interface on a socketed part
on a functional tester at the maximum frequencies in
information are tested at core-to-L2 divisors of two or greater.
L2 input and output signals are latched or enabled, respectively, by the internal L2CLK (which is SYSCLK
multiplied up to the core frequency and divided down to the L2CLK frequency). In other words, the AC timings in
Table 10
the board trace by L2SYNC_OUT, L2SYNC_IN only controls the output phase of L2CLK_OUTA and
L2CLK_OUTB which are used to latch or enable data at the SRAMs. However, since in a closed loop system
L2SYNC_IN is held in phase-alignment with the internal L2CLK, the signals in
signal rather than the not-externally-visible internal L2CLK. During manufacturing test, these times are actually
measured relative to SYSCLK.
18
At recommended operating conditions (see
L2CLK frequency
L2CLK cycle time
L2CLK duty cycle
Internal DLL-relock time
DLL capture window
L2CLK_OUT
output-to-output skew
for example core and L2 frequencies at various divisors.
are entirely independent of L2SYNC_IN. In a closed loop system, where L2SYNC_IN is driven through
L2 Clock AC Specifications
Parameter
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Table 9. L2CLK Output AC Timing Specifications
t
CHCL
Symbol
t
L2CSKW
f
t
Table
L2CLK
L2CLK
Table 9
—
—
/t
L2CLK
3)
is specified by the maximum delay of the internal DLL. The variable-tap
Table 9
Figure
Min
133
640
2.5
—
0
400 MHz
is the core frequency divided by one. Very few L2 SRAM
50
7.
Table
Max
400
7.5
10
50
—
9. Therefore, functional operation and AC timing
Min
133
640
2.5
—
0
450 MHz
Table 9
50
Max
400
7.5
10
50
—
provides the potential range of L2CLK
Min
133
640
2.5
Table 10
—
0
500 MHz
50
Max
400
7.5
10
50
—
are referenced to this
Freescale Semiconductor
L2CLK
MHz
Unit
ns
ns
ps
%
Notes
1, 4
—
2
3
5
6