FW80200M733SL678 Intel, FW80200M733SL678 Datasheet - Page 15

• Manufacturer Part Number: FW80200M733SL678
• Description: IC I/O PROCESSOR 733MHZ 241-BGA
• Manufacturer: Intel

Specifications of FW80200M733SL678

• Rohs Status: RoHS non-compliant
• Processor Type: I/O
• Features: XScale Core
• Speed: 733MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 241-BGA
• Other names: 844850

Datasheet - Commercial and Extended Temperature (80200T)
Table 4.
Signal Pin Description (Sheet 2 of 2)
1. For signals D, DCB, BE# during Hold mode, these continue to carry valid data until all pending transactions from the 80200
HOLD
IRQ#
LOCK/LEN[1]
LOWVPP
LOWVCC
MCLK
N/C
PLLCFG
(Config. Pin)
PWRSTATUS[1:
0]
RESET#
RESETOUT#
W_R#/LEN[0]
have been completed. Then these signals float.
Name
Count
1
1
1
1
1
1
8
1
2
1
1
1
Intel
®
Rst(X)
Hld(Q)
Slp(Q)
Hld(Q)
Rst(X)
Hld(Z)
Slp(X)
Rst(0)
Rst(0)
Hld(Z)
Slp(X)
Slp(1)
Type
N/C
80200 Processor based on Intel
O
O
O
O
I
I
I
I
I
I
I
HOLD: Requests the Intel
signals.
Interrupt Request: When IRQs are enabled, the processor
responds to a low level on this input by taking the IRQ interrupt
exception.
Atomic Transaction Indicator/Length:
During the first cycle of the issue phase, this signal indicates the
current transaction is part of an atomic read-write pair.
During the second cycle of the issue phase, this signal is the
middle bit of a value which indicates the length of the transaction.
Pad Voltage Level: When tied to the same level as V
indicates voltage for the device pins (V
When tied to V
than or equal to 2.5V.
Core Voltage Level: When tied to the same level as V
indicates voltage for the core (V
V
Memory Clock: all bus signals must be synchronous to this clock.
NO CONNECT. Do not make electrical connections to these balls.
PLL Configuration: While RESET# is asserted, this pin is
sampled by the 80200 to select the initial clock multiplier value.
When tied high, the initial clock multiplier is 6. When tied low, the
initial clock multiplier is 3. This signal must be tied to a valid level at
all times. When using the Intel 80312 I/O companion chip, this
signal must be tied high.
Power Status Indicator: Indicates the current power mode of the
Intel
indicate the current power state:
00 for Normal
01 for Idle
10 for Reserved (Do Not Use)
11 for Sleep
Reset: When asserted, this signal resets the processor. This signal
must be asserted for at least 32 consecutive MCLK cycles to
achieve a valid reset.
Reset Status Output: This signal is asserted when the processor
detects RESET#, and deasserts when the processor has
completed resetting.
Address Strobe/Length:
During the first cycle of the issue phase, this signal indicates that
the current transaction is a read (W_R# = 0) or a write (W_R# = 1).
During the second cycle of the issue phase, this signal is the LSB
of a value which indicates the length of the transaction.
SS
, indicates voltage for the core is greater than or equal to 1.0V.
®
80200 processor. This signal contains an encoded value to
SS
, indicates voltage at the device pins is greater
®
Description
80200 processor to float shared bus
January 2003
CC
®
XScale
) is less than 1.0V. When tied to
CCP
Package Information
) is less than 2.5V.
™
Microarchitecture
CCP
CCP
,
,
15