MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 434

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Serial Communication Controllers (SCCs)
7.10.1 SCC Overview
The QUICC has four SCCs that can be configured independently to implement different pro-
tocols. Together, they can be used to implement bridging functions, routers, gateways, and
interface with a wide variety of standard wide area networks, local area networks, and pro-
prietary networks. The SCCs have many physical interface options such as interfacing to
TDM buses, ISDN buses, and standard modem interfaces (see 7.8 Serial Interface with
Time Slot Assigner).
On the QUICC, the SCC does not include the physical interface, but it is the logic which for-
mats and manipulates the data obtained from the physical interface. That is why the SI sec-
tion is described separately. The choice of protocol is independent of the choice of physical
interface.
The SCC is described in terms of the protocol that it is chosen to run. When an SCC is pro-
grammed to a certain protocol, it implements a certain level of functionality associated with
that protocol. For most protocols, this corresponds to portions of the link layer (layer 2 of the
seven-layer ISO model). Many functions of the SCC are common to all of the protocols.
These functions are described first in the SCC description. Following that, the specific imple-
mentation details that make one protocol different from the others are discussed, beginning
with the UART protocol. Thus, the reader should read from this point up to the UART proto-
col, and then skip to the particular protocol desired. Since the SCCs use similar data struc-
tures across all protocols, the reader's learning time will decrease dramatically after
understanding the first protocol.
Each SCC supports a number of protocols: HDLC/SDLC, HDLC bus, BISYNC, asynchro-
nous or synchronous start/stop (UART), totally transparent operation, and AppleTalk (i.e.,
LocalTalk). In addition, Ethernet is available on SCC1 of the Ethernet version of the QUICC.
Although the protocol that is chosen usually applies to both the SCC transmitter and
receiver, the SCCs have an option of running one-half of the SCC with transparent operation
while the other half runs the standard protocol.
Each of the internal clocks (RCLK, TCLK) for each SCC can be programmed with either an
external or internal source. The internal clocks can originate from one of four baud rate gen-
erators or one of four external clock pins. These clocks may be as fast as a 1:2 ratio of the
system clock (i.e., 12.5 MHz); however, the SCC’s ability to support a sustained bit stream
depends on the protocol as well as other factors. See Appendix A Serial Performance for
more details.
Associated with each SCC is a digital phase-locked loop (DPLL) for external clock recovery.
The clock recovery options include NRZ, NRZI, FM0, FM1, Manchester, and Differential
Manchester. The DPLL may be configured to NRZ operation in order to pass the clocks and
data to/from the SCCs without modifying them.
7-110
The performance figures listed in the key features assume a 25-
MHz system clock.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
MOTOROLA