XPC850DEZT50BT Freescale Semiconductor, XPC850DEZT50BT Datasheet - Page 62

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XPC850DEZT50BT

Manufacturer Part Number
XPC850DEZT50BT
Description
IC POWER PC MPU 80MHZ 256-PBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of XPC850DEZT50BT

Processor Type
MPC8xx PowerQUICC 32-Bit
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
256-PBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Other names
Q1146100
XPC8500DEZT50BT
XPC8500DEZT50BT

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CPM Electrical Characteristics
Table 25
Figure 61
62
1
Num
200
200
202
203
204
205
206
207
208
209
210
211
The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1.
SDA
SCL
SCL frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) * pre_scaler * 2).
provides the I
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
shows the I
SCL clock frequency (slave)
SCL clock frequency (master)
Bus free time between transmissions
Low period of SCL
High period of SCL
Start condition setup time
Start condition hold time
Data hold time
Data setup time
SDL/SCL rise time
SDL/SCL fall time
Stop condition setup time
1
The ratio SyncClk/(BRGCLK/pre_scaler) must be greater or equal to 4/1.
Num
SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) * pre_scaler * 2).
205
210
211
202
2
SDL/SCL fall time
Stop condition setup time
Characteristic
C bus timing.
2
206
C (SCL > 100 KHz) timings.
Table 24. I
203
Table 25. I
Figure 61. I
Characteristic
1
2
C Timing (SCL < 100 KH
2
207
C Timing (SCL > 100 KH
fSCL
fSCL
Expression
2
209
C Bus Timing Diagram
204
210
BRGCLK/16512
1/2(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(40 * fSCL)
Z
) (
Min
0
0
CONTINUED
All Frequencies
All Frequencies
Z
4.70
Min
)
)
208
300.00
1/(10 * fSCL)
1/(33 * fSCL)
BRGCLK/48
BRGCLK/48
Max
Max
Freescale Semiconductor
211
Unit
µs
ns
Unit
Hz
Hz
s
s
s
s
s
s
s
s
s
s

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