MC68HC000FN16 Freescale Semiconductor, MC68HC000FN16 Datasheet - Page 60

• Manufacturer Part Number: MC68HC000FN16
• Description: IC MPU 32BIT 16MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC000FN16

• Processor Type: M680x0 32-Bit
• Speed: 16MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

The timing diagram in Figure 5-15 shows that the bus request is negated at the time that
an acknowledge is asserted. This type of operation applies to a system consisting of a
processor and one other device capable of becoming bus master. In systems having
several devices that can be bus masters, bus request lines from these devices can be
wire-ORed at the processor, and more than one bus request signal could occur.
The bus grant signal is negated a few clock cycles after the assertion of the bus grant
acknowledge signal. However, if bus requests are pending, the processor reasserts bus
grant for another request a few clock cycles after bus grant (for the previous request) is
negated. In response to this additional assertion of bus grant, external arbitration circuitry
selects the next bus master before the current bus master has completed the bus activity.
The timing diagram in Figure 5-15 also applies to a system consisting of a processor and
one other device capable of becoming bus master. Since the 48-pin version of the
MC68008 and the MC68EC000 does not recognize a bus grant acknowledge signal, this
processor does not negate bus grant until the current bus master has completed the bus
activity.
5.2.1 Requesting The Bus
External devices capable of becoming bus masters assert BR to request the bus. This
signal can be wire-ORed (not necessarily constructed from open-collector devices) from
any of the devices in the system that can become bus master. The processor, which is at
a lower bus priority level than the external devices, relinquishes the bus after it completes
the current bus cycle.
The bus grant acknowledge signal on all the processors except the 48-pin MC68008 and
MC68EC000 helps to prevent the bus arbitration circuitry from responding to noise on the
5-14
FC2–FC0
A19–A0
DTACK
D7–D0
CLK
R/W
DS
BR
BG
AS
PROCESSOR
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Figure 5-16. 2-Wire Bus Arbitration Timing Diagram
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
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Freescale Semiconductor, Inc.
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Go to: www.freescale.com
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PROCESSOR
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MOTOROLA