A80960CF33 Intel, A80960CF33 Datasheet - Page 20

• Manufacturer Part Number: A80960CF33
• Description: IC MPU I960CF 33MHZ 168-PGA
• Manufacturer: Intel

Specifications of A80960CF33

• Processor Type: i960
• Features: CF suffix, 32-Bit with DMA, 4K Cache
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 168-PGA
• Family Name: 80960
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: 0C to 100C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 168
• Package Type: CPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 803084

80960-40, -33, -25
3.3.2
20
Table 8.
80960CF PQFP Pinout (80960CF-33 and -25 Only)
Table 8
80960CF PQFP pinout as viewed from the top side. See
page 26
80960CF PQFP Pinout—In Signal Order (80960CF-33 and -25 Only)
Signal
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A10
A11
Address Bus
A9
A8
A7
A6
A5
A4
A3
A2
and
for specifications and recommended connections.
Table 9
153
152
151
145
144
143
142
141
139
138
137
136
134
133
132
130
129
128
124
123
122
120
Pin
119
118
117
116
114
113
112
111
present the 80960CF pin names with package location.
Signal
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Data Bus
Pin
186
187
188
189
191
192
194
195
10
13
14
15
17
18
19
21
22
23
25
26
27
33
34
35
36
11
3
4
5
6
8
9
SUP
BOFF
READY
BTERM
HOLDA
BLAST
Signal
BREQ
LOCK
HOLD
WAIT
DT/R
DMA
ADS
DEN
BE3
BE2
BE1
BE0
W/R
D/C
Bus Control
Pin
176
175
172
170
164
178
182
184
162
169
163
167
156
181
179
155
159
160
158
40
Section 4.0, “Electrical Specifications” on
2, 7, 16, 24, 30, 38,
39, 49, 56, 70, 75,
77, 81, 83, 88, 89,
92, 98, 105, 109,
110, 121, 125, 131,
135, 147, 150, 161,
165, 173, 174, 185,
196
1, 12, 20, 28, 32, 37,
44, 50, 61, 71, 79,
82, 96, 99, 103, 115,
127, 140, 148, 154,
168, 171, 180, 190
29, 31, 41, 42, 47,
48, 51, 52, 53, 54,
55, 73, 76, 80, 84,
86, 90, 97, 104, 126,
146, 149, 157, 166,
177, 183, 193
Processor Control
CLKMOD
RESET
PCLK2
PCLK1
V
STEST
CLKIN
Signal
ONCE
FAIL
CCPLL
No Connect
E
Location
Location
Location
V
V
CC
SS
Pin
91
45
46
43
87
85
74
78
72
Figure 4
EOP/TC3
EOP/TC2
EOP/TC1
EOP/TC0
DREQ3
DREQ2
DREQ1
DREQ0
DACK3
DACK2
DACK1
DACK0
Signal
XINT7
XINT6
XINT5
XINT4
XINT3
XINT2
XINT1
XINT0
NMI
shows the
Datasheet
I/O
107
106
102
101
100
108
Pin
60
59
58
57
65
64
63
62
69
68
67
66
95
94
93