TN80C188EA20 Intel, TN80C188EA20 Datasheet - Page 12

• Manufacturer Part Number: TN80C188EA20
• Description: IC MPU 16-BIT 5V 20MHZ 68-PLCC
• Manufacturer: Intel

Specifications of TN80C188EA20

• Rohs Status: RoHS non-compliant
• Processor Type: 80C188
• Features: EA suffix, 16-Bit, Extended Temp
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Other names: 803497

80C186EA 80C188EA 80L186EA 80L188EA
NOTE
Pin names in parentheses apply to the 80C188EA and 80L188EA
12
A18 16
A19 S6–A16
(A19–A8)
S2 0
ALE QS0
BHE
(RFSH)
RD QSMD
Name
Pin
Type
Pin
O
O
O
O
O
Input
Type
Output
Table 3 Pin Descriptions (Continued)
States
R(WH)
H(Z)
R(Z)
P(X)
H(Z)
R(Z)
H(0)
R(0)
H(Z)
R(Z)
P(X)
H(Z)
P(1)
P(0)
P(1)
These pins provide multiplexed Address during the address
phase of the bus cycle Address bits 16 through 19 are
presented on these pins and can be latched using ALE
A18 16 are driven to a logic 0 during the data phase of the bus
cycle On the 8-bit bus versions A15 – A8 provide valid address
information for the entire bus cycle Also during the data
phase S6 is driven to a logic 0 to indicate a CPU-initiated bus
cycle or logic 1 to indicate a DMA-initiated bus cycle or a
refresh cycle
Bus cycle Status are encoded on these pins to provide bus
transaction information S2 0 are encoded as follows
S2
Address Latch Enable output is used to strobe address
information into a transparent type latch during the address
phase of the bus cycle In Queue Status Mode QS0 provides
queue status information along with QS1
Byte High Enable output to indicate that the bus cycle in
progress is transferring data over the upper half of the data
bus BHE and A0 have the following logical encoding
On the 80C188EA 80L188EA RFSH is asserted low to
indicate a Refresh bus cycle
ReaD output signals that the accessed memory or I O device
must drive data information onto the data bus Upon reset this
pin has an alternate function As QSMD it enables Queue
Status Mode when grounded In Queue Status Mode the
ALE QS0 and WR QS1 pins provide the following information
about processor instruction queue interaction
0
0
0
0
1
1
1
1
QS1
A0
0
0
1
1
0
0
1
1
S1
0
0
1
1
0
0
1
1
BHE
QS0
S0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
Interrupt Acknowledge
Read I O
Write I O
Processor HALT
Queue Instruction Fetch
Read Memory
Write Memory
Passive (no bus activity)
Encoding (For 80C186EA 80L186EA Only)
Word Transfer
Even Byte Transfer
Odd Byte Transfer
Refresh Operation
No Queue Operation
First Opcode Byte Fetched from the Queue
Subsequent Byte Fetched from the Queue
Empty the Queue
Bus Cycle Initiated
Description
Queue Operation
12