TS80C188EB20 Intel, TS80C188EB20 Datasheet
TS80C188EB20
Specifications of TS80C188EB20
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TS80C188EB20 Summary of contents
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... Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. ...
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High-Integration Embedded Processors CONTENTS INTRODUCTION CORE ARCHITECTURE Bus Interface Unit Clock Generator 80C186EC PERIPHERAL ARCHITECTURE Interrupt Control Unit Timer Counter Unit Serial Communications Unit Chip-Select Unit I O Port Unit Refresh Control Unit Power ...
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NOTE Pin names in parentheses apply to the 80C188EB 80L188EB Figure 1 80C186EB 80C188EB Block Diagram 80C186EB 80C188EB 80L186EB 80L188EB 272433 – ...
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INTRODUCTION Unless specifically noted all references to the 80C186EB apply to the 80C188EB 80L186EB and 80L188EB References to pins that differ between the 80C186EB 80L186EB and the 80C188EB 80L188EB are given in parentheses The ‘‘L’’ in ...
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Crystal Connection NOTE The L C network is only required when using a third overtone crystal The following parameters are recommended when choosing a crystal Temperature Range Application Specific ESR (Equivalent Series Resistance) C0 (Shunt Capacitance of ...
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PCB PCB Function Offset Offset 00H Reserved 40H 02H End Of Interrupt 42H Timer2 Compare 04H Poll 44H 06H Poll Status 46H Timer2 Control 08H Interrupt Mask 48H 0AH Priority Mask 4AH 0CH In-Service 4CH 0EH ...
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Serial Communications Unit The Serial Control Unit (SCU) of the 80C186EB con- tains two independent channels Each channel is identical in operation except that only channel 0 is supported by the integrated interrupt controller (channel 1 has an external interrupt ...
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... Leaded Chip Carrier (PLCC) package, Shrink Quad Flat Pack (SQFP), and Quad Flat Pack (QFP) pack- age. For complete package specifications and infor- mation, see the Intel Packaging Outlines and Dimen- sions Guide (Order Number: 231369). Prefix Identification With the extended temperature range, operational ...
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Table 2 Pin Description Nomenclature Symbol P Power Pin (Apply G Ground (Connect Input Only Pin O Output Only Pin I O Input Output Pin S(E) Synchronous Edge Sensitive S(L) Synchronous Level Sensitive A(E) Asynchronous Edge Sensitive ...
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Pin Pin Input Output Name Type Type States CLKIN I A(E) OSCOUT O H(Q) R(Q) P(Q) CLKOUT O H(Q) R(Q) P(Q) RESIN I A(L) RESOUT O H(0) R(1) PDTMR I ...
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Table 3 Pin Descriptions (Continued) Pin Pin Input Output Name Type Type States A18 A(L) H(Z) A19 ONCE R(WH) (A15 A8) P(X) (A18 16) (A19 ONCE H(Z) R(Z) P(1) ALE O H(0) R(0) P(0) ...
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Table 3 Pin Descriptions (Continued) Pin Pin Input Output Name Type Type States H(Z) R(Z) LOCK O H(Z) R(WH) HOLD I A(L) HLDA O NCS ERROR I A(L) (N ...
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Table 3 Pin Descriptions (Continued) Pin Pin Input Name Type Type T0OUT O T1OUT T0IN I A(L) T1IN A(E) INT0 I A(E L) INT1 INT4 INT2 INTA0 I O A(E L) INT3 INTA1 A( ...
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PINOUT Tables 4 and 5 list the 80C186EB 80C188EB pin names with package location for the 84-pin Plastic Leaded Chip Carrier (PLCC) component Figure 5 depicts the complete 80C186EB 80C188EB pinout (PLCC package) as viewed ...
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Table 5 PLCC Package Locations with Pin Name Location Name Location ERROR ( ALE 27 7 BHE (RFSH ...
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NOTE: This is the FPO number location (indicated by X’s). Pin names in parentheses apply to the 80C188EB/80L188EB. Figure 4. 84-Pin Plastic Leaded Chip Carrier Pinout Diagram 16 272433– 5 ...
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Table 6 QFP Pin Name with Package Location Address Data Bus Bus Control Name Location Name AD0 10 ALE AD1 15 BHE (RFSH) AD2 17 S0 AD3 19 S1 AD4 21 S2 AD5 23 RD AD6 25 WR AD7 27 ...
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Table 7 QFP Package Location with Pin Names Location Name Location 1 CTS0 21 2 TXD0 22 3 RXD0 BCLK0 SINT1 CTS1 26 7 ...
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NOTE: This is the FPO number location (indicated by X’s). Pin names in parentheses apply to the 80C188EB/80L188EB. Figure 5. Quad Flat Pack Pinout Diagram 80C186EB/80C188EB, 80L186EB/80L188EB 272433– ...
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Table 8 SQFP Pin Functions with Location AD Bus Bus Control AD0 47 ALE AD1 52 BHE (RFSH ) AD2 54 S0 AD3 56 S1 AD4 58 S2 AD5 60 RD AD6 62 WR AD7 64 ...
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... NOTE: XXXXXXXXC indicates Intel FPO number. Pin names in parentheses apply to the 80C188EB/80L188EB. 80C186EB/80C188EB, 80L186EB/80L188EB Figure 6. SQFP Package 272433– ...
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PACKAGE THERMAL SPECIFICATIONS The 80C186EB 80L186EB is specified for operation when T (the case temperature) is within the range 100 C (PLCC package 114 C (QFP package) T ...
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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Storage Temperature Case Temp under Bias Supply Voltage with Respect Voltage on other Pins with Respect ...
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DC SPECIFICATIONS (80C186EB 80C188EB) Symbol Parameter V Supply Voltage CC V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH V Input Hysterisis on RESIN HYR ...
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DC SPECIFICATIONS (80L186EB16) Symbol Parameter V Supply Voltage CC V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH V Input Hysterisis on RESIN HYR I Input Leakage Current for ...
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DC SPECIFICATIONS (80L186EB13 80L188EB13 Symbol Parameter V Supply Voltage CC V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH V Input Hysterisis on RESIN HYR ...
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I VERSUS FREQUENCY AND VOLTAGE CC The current (I ) consumption of the processor is CC essentially composed of two components I I CCS I is the quiescent current that represents internal PD device leakage and is measured with all ...
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AC SPECIFICATIONS AC Characteristics 80C186EB25 Symbol Parameter INPUT CLOCK T CLKIN Frequency F T CLKIN Period C T CLKIN High Time CH T CLKIN Low Time CL T CLKIN Rise Time CR T CLKIN Fall Time ...
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AC SPECIFICATIONS AC Characteristics 80C186EB25 Symbol SYNCHRONOUS INPUTS T TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 CHIS T TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0 CHIH T AD15 ...
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AC SPECIFICATIONS AC Characteristics 80C186EB20 80C186EB13 Symbol Parameter INPUT CLOCK T CLKIN Frequency F T CLKIN Period C T CLKIN High Time CH T CLKIN Low Time CL T CLKIN Rise Time CR T CLKIN Fall ...
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AC SPECIFICATIONS AC Characteristics 80C186EB20 80C186EB13 Symbol Parameter SYNCHRONOUS INPUTS T TEST NMI INT4 0 BCLK1 0 T1 0IN CHIS READY CTS1 TEST NMI INT4 0 BCLK1 0 T1 0IN CHIH READY CTS1 0 ...
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AC SPECIFICATIONS AC Characteristics 80L186EB16 Symbol Parameter INPUT CLOCK T CLKIN Frequency F T CLKIN Period C T CLKIN High Time CH T CLKIN Low Time CL T CLKIN Rise Time CR T CLKIN Fall Time ...
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AC SPECIFICATIONS AC Characteristics 80L186EB16 Symbol SYNCHRONOUS INPUTS T TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 CHIS T TEST NMI INT4 0 T1 0IN BCLK1 0 READY CTS1 0 CHIH T AD15 ...
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AC SPECIFICATIONS AC Characteristics 80L186EB13 Symbol Parameter INPUT CLOCK T CLKIN Frequency r T CLKIN Period C T CLKIN High Time CH T CLKIN Low Time CL T CLKIN Rise Time CR T CLKIN Fall Time ...
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AC SPECIFICATIONS AC Characteristics 80L186EB13 80L186EB8 Symbol Parameter SYNCHRONOUS INPUTS T TEST, NMI, INT4:0, CHIS BCLK1 0 T1 0IN READY CTS1 TEST, NMI, INT4:0, T1:0IN, CHIH BCLK1 0 READY CTS1 0 T AD15:0 (AD7:0), ...
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AC SPECIFICATIONS (Continued) Relative Timings (80C186EB25 20 13 80L186EB16 13 8) Symbol Parameter RELATIVE TIMINGS T ALE Rising to ALE Falling LHLL T Address Valid to ALE Falling AVLL T Chip Selects Valid to ALE Falling ...
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AC SPECIFICATIONS (Continued) Serial Port Mode 0 Timings (80C186EB25 20 13 80L186EB16 13 8) Symbol Parameter T TXD Clock Period XLXL T TXD Clock Low to Clock High (n XLXH T TXD Clock Low to Clock High (n XLXH T ...
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AC TEST CONDITIONS The AC specifications are tested with the 50 pF load shown in Figure 7 See the Derating Curves section to see how timings vary with load capacitance Specifications are measured at the V ...
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NOTE 20% V Float 80 Figure 9 Output Delay and Float Waveform Figure 10 Input Setup and Hold 80C186EB 80C188EB 80L186EB 80L188EB 272433 –10 272433 –11 39 ...
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NOTE Pin names in parentheses apply to 80C188EB 80L188EB Figure 11 Relative Signal Waveform Figure 12 Serial Port Mode 0 Waveform 40 272433 –12 272433 –13 ...
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DERATING CURVES TYPICAL OUTPUT DELAY VARIATIONS VERSUS LOAD CAPACITANCE TYPICAL RISE AND FALL VARIATIONS VERSUS LOAD CAPACITANCE 80C186EB 80C188EB 80L186EB 80L188EB 272433 –14 Figure 13 272433 –15 Figure 14 41 ...
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RESET The processor will perform a reset operation any time the RESIN pin active The RESIN pin is actually synchronized before it is presented internally which means that the clock must be operating before a reset ...
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Figure 15 Cold Reset Waveforms 43 ...
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Figure 16 Warm Reset Waveforms 44 ...
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BUS CYCLE WAVEFORMS Figures 17 through 23 present the various bus cy- cles that are generated by the processor What is shown in the figure is the relationship of the various NOTE Pin names in parentheses apply to 80C188EB 80L188EB ...
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NOTE Pin names in parentheses apply to 80C188EB 80L188EB Figure 18 Write Cycle Waveforms 46 272433 –19 ...
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NOTE The address driven is typically the location of the next instruction prefetch Under a majority of instruction sequences the AD15 0 (AD7 0) bus will float while the A19 16 (A19 8) bus remains driven and all bus control ...
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NOTE Pin names in parentheses apply to 80C188EB 80L188EB Figure 20 Interrupt Acknowledge Cycle Waveform 48 272433 –21 ...
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NOTE Pin names in parentheses apply to 80C188EB 80L188EB Figure 21 HOLD HLDA Waveforms 80C186EB 80C188EB 80L186EB 80L188EB 272433 –22 49 ...
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NOTES 1 READY must be low by either edge to cause a wait state 2 Lighter lines indicate READ cycles darker lines indicate WRITE cycles Pin names in parentheses apply to 80C188EB 80L188EB Figure 22 Refresh ...
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NOTES 1 READY must be low by either edge to cause a wait state 2 Lighter lines indicate READ cycles darker lines indicate WRITE cycles Pin names in parentheses apply to 80C188EB 80L188EB Figure 23 Ready Waveforms 80C186EB 80C188EB 80L186EB ...
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EXECUTION TIMINGS A determination of program execution timing must consider the bus cycles necessary to prefetch in- structions as well as the number of execution unit cycles necessary to execute instructions The fol- lowing instruction timings ...
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INSTRUCTION SET SUMMARY Function DATA TRANSFER MOV Move e Register to Register Memory Register memory to register Immediate to register memory ...
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INSTRUCTION SET SUMMARY Function DATA TRANSFER (Continued) SEGMENT Segment Override ...
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INSTRUCTION SET SUMMARY Function ARITHMETIC (Continued) IMUL Integer multiply (signed Register-Byte Register-Word Memory-Byte Memory-Word IMUL Integer Immediate multiply (signed) DIV Divide (unsigned) ...
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INSTRUCTION SET SUMMARY Function LOGIC (Continued) XOR Exclusive or e Reg memory and register to either Immediate to register memory ...
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INSTRUCTION SET SUMMARY Function CONTROL TRANSFER (Continued) RET Return from CALL e Within segment Within seg adding immed Intersegment ...
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INSTRUCTION SET SUMMARY Function PROCESSOR CONTROL CLC Clear carry CMC Complement carry STC Set carry ...
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ERRATA An 80C186EB 80L186EB with a STEPID value of 0001H has the following known errata A device with a STEPID of 0001H can be visually identified by the presence of an ‘‘A’’ alpha character next to the FPO number The ...