Z8018008VSC Zilog, Z8018008VSC Datasheet - Page 24

• Manufacturer Part Number: Z8018008VSC
• Description: IC 8MHZ Z180 CMOS ENH MPU 68PLCC
• Manufacturer: Zilog

Specifications of Z8018008VSC

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Number Of Timers: 2 bit
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3013

PS014004-1106
INT
HALT and Low-Power Operating Modes—
respect to activity and power consumption:
•
•
•
•
•
Normal Operation—
functions and portions of the device are active, and the
HALT Mode—
processor continually fetches the following opcode but does not execute it, and drives the
HALT
granting to external masters, and DRAM refresh can occur and all on-chip I/O devices
continue to operate including the DMA channels.
The Z80180 leaves
enabled on-chip source, an external request on
INT1
HALT
to wait for another interrupt, or can examine the new state of the system/application and
respond appropriately.
MREQ
A
HALT
i
, NMI
0
–A
RD
M1
Normal Operation
HALT
IOSTOP
SLEEP
SYSTEM STOP mode
φ
19
, or
HALT Opcode Fetch Cycle
,
instruction; at that point the program can either branch back to the
ST
HALT Opcode Address
T
INT2
2
and
mode
mode
mode
. In case of an interrupt, the return address is the instruction following the
M1
This mode is entered by the
pins all Low. The oscillator and
HALT
T
3
The Z80180 processor is fetching and running a program. All enabled
Figure 13. HALT Timing
mode in response to a Low on
T
1
HALT Mode
T
HALT Opcode Address + 1
HALT
2
The Z80180 can operate in five modes with
NMI
instruction. Thereafter, the Z80180
PHI
, or an enabled external request on
T
3
pin remain active, interrupts and bus
HALT
RESET
pin is High.
, on to an interrupt from an
T
1
Interrupt
Acknowledge Cycle
Microprocessor Unit
HALT
T
2
Architecture
instruction
Z80180
INT0
,
18