668-0010 Rabbit Semiconductor, 668-0010 Datasheet - Page 141

• Manufacturer Part Number: 668-0010
• Description: IC MPU RABIT3000 55.5MHZ 128LQFP
• Manufacturer: Rabbit Semiconductor

Specifications of 668-0010

• Rohs Status: RoHS non-compliant
• Processor Type: Rabbit 3000 8-Bit
• Speed: 55.5MHz
• Voltage: 2.5V, 2.7V, 3V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Features: -
• Other names: 316-1016

Chapter 17 Serial Ports A – D
Bit(s)
1:0
7
6
5
4
3
2
Serial Port x Status Register
(Asynchronous Mode Only)
Value
00
0
1
0
1
0
1
0
0
1
0
1
The receive data register is empty—no input character is ready.
There is a byte in the receive buffer. The transition from “0” to “1” sets the
receiver interrupt request flip-flop. The interrupt FF is cleared when the character
is read from the data buffer. The interrupt FF will be immediately set again if
there are more characters available in the FIFO or shift register to be transferred
into the data buffer.
The byte in the receive buffer is data, received with a valid stop bit.
The address bit or 9th (8th) bit received. This bit is set if the character in the
receiver data register has a 9th (8th) bit. This bit is cleared and should be checked
before reading a data register since a new data value with a new address bit may
be loaded immediately when the data register is read.
The byte in the receive buffer is an address, or a byte with a framing error. If an
address bit is not expected. If the data in the buffer is all zeros, this may be a
break.
The receive buffer was not overrun.
The receive buffer was overrun. This bit is cleared by reading the receive buffer.
This bit is always zero in the asynchronous mode
The transmit buffer is empty.
The
full, that is, a byte is written to the serial port data register. It is cleared when a
byte is transferred to the transmitter shift register or FIFO, or a write operation is
performed to the serial port status register. This bit will request an interrupt on
the transition from 1 to 0 if interrupts are enabled. Transmit interrupts are cleared
when the transmit buffer is written, or any value (which will be ignored) is
written to this register.
The transmitter is idle.
Transmit busy bit. This bit is set if the transmit shift register is busy sending data.
It is set on the falling edge of the start bit, which is also the clock edge that
transfers data from the transmit data register to the transmit shift register. The
transmit busy bit is cleared at the end of the stop bit of the character sent. This bit
will cause an interrupt to be latched when it goes from busy to not busy status
after the last character has been sent (there are no more data in the transmit data
register).
These bits are always zero in the asynchronous mode.
t
ransmit data buffer is full. This bit is set when the transmit data register is
(SASR)
(SBSR)
(SCSR)
(SDSR)
Description
(Address = 0x00D3)
(Address = 0x00C3)
(Address = 0x00E3)
(Address = 0x00F3)
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