TS68040VR25A Atmel, TS68040VR25A Datasheet - Page 38

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TS68040VR25A

Manufacturer Part Number
TS68040VR25A
Description
IC MPU 32BIT 25MHZ 179PGA
Manufacturer
Atmel
Datasheet

Specifications of TS68040VR25A

Processor Type
68000 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
179-PGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Figure 21. Cache Organization Overview
The caches are accessed by physical addresses from the on-chip MMUs. The transla-
tion of the upper bits of the logical address occurs concurrently with the accesses into
the set array in the cache by the lower address bits. The output of the ATC is compared
with the tag field in the cache to determine if one of the lines in the selected set matches
the translated physical address. If the tag matches and the entry is valid, then the cache
has a hit.
If the cache hits and the access is a read, the appropriate long word from the cache line
is multiplexed onto the appropriate internal bus. If the cache hits and the access is a
write, the data, regardless of size, is written to the appropriate portion of the correspond-
ing longword entry in the cache.
When a data cache miss occurs and a previously valid cache line is needed to cache
the new line, any dirty data in the old line will be internally buffered and copied back to
memory after the new cache line has been loaded.
Pushing of dirty data can be forced by the CPUSH instruction.
TS68040
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2116A–HIREL–09/02

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