XS1-L02A-QF124-I4 XMOS, XS1-L02A-QF124-I4 Datasheet - Page 12

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XS1-L02A-QF124-I4

Manufacturer Part Number
XS1-L02A-QF124-I4
Description
IC MPU 32BIT DUAL CORE 124QFN
Manufacturer
XMOS

Specifications of XS1-L02A-QF124-I4

Processor Type
XCore 32-Bit
Speed
400MHz
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
124-TFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
880-1005
XS1-L02-FB144-I4
XS1-L2 124QFN Datasheet (1.5)
XCore, Switch and OTP for such actions as loading code and debugging. Both TAPs
which optionally add in additional TAPs into the JTAG chain for each of the Switch,
XCore and OTP. The XCore TAP allows register read/write commands to be made for
A diagram of the JTAG chain structure is shown below:
The JTAG device identification register can be read by using the IDCODE instruction.
The JTAG usercode register can be read by using the USERCODE instruction. Its
have an instruction register length of 4. From reset, the chip TAP is in BYPASS so
simply presents an extra 1-bit into the scan chain when shifting data.
If access to the XCore/Switch/OTP is required, the ChipTAP sets internal multiplexers
program loading/debug.
3.6.1 Device identification register
Its contents are specified as follows:
3.6.2 Usercode register
contents are specified as follows:
Bit31
0
Bit31
0
Version
0
0
0
0
0
0
0
0
OTP User ID
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Part Number
Unused
0
0
0
0
Device identification register
XCore0
www.xmos.com
0
0
Usercode register
0
2
0
1
0
0
0
1
0
0
2
8
1
0
0
0
0
0
Silicon Revision
1
0
6
0
1
0
Manufacturer Identity
0
0
0
0
0
0
3
0
1
0
XCore1
XS1-L2
1
0
0
0
0
0
3
0
1
0
12/28
Bit0
Bit0
1
1
0

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