MC68LC060RC50 Freescale Semiconductor, MC68LC060RC50 Datasheet - Page 226
MC68LC060RC50
Manufacturer Part Number
MC68LC060RC50
Description
IC MPU 32BIT 68K 50MHZ 206-PGA
Manufacturer
Freescale Semiconductor
Specifications of MC68LC060RC50
Processor Type
M680x0 32-Bit
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
206-PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
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7.13 RESET OPERATION
An external device asserts the reset input signal (RSTI) to reset the processor. When power
is applied to the system, external circuitry should assert RSTI for a minimum of ten BCLK
cycles after V
on reset operation, illustrating the relationships among V
signals. CLK is required to be stable by the time V
ification. CLK should start oscillating as V
internal to the part caused by the random manner in which internal flip-flops power-up. RSTI
is internally synchronized for two BCLKs before being used and must meet the specified
MOTOROLA
CC
ARBITRATION
* AM indicates the alternate bus master.
ATTRIBUTES
TRANSFER
is within tolerance. Figure 7-48 is a functional timing diagram of the power-
D31–D0
AM_BG*
AM_BR*
A31–A0
SNOOP
STATE
BCLK
BUS
BTT
TT1
BR
BG
TA
BB
TS
END-TEN
C1
Figure 7-47. Snooped Bus Cycle
AM-IMP
M68060 USER’S MANUAL
C2
SNOOP
C3
CC
is ramped up in order to clear out contention
AM-EXP
ALTERNATE
MASTER
C4
CC
AM-EXP
reaches the minimum operating spec-
C5
CC
AM-EXP
, RSTI, mode selects, and bus
C6
PROCESSOR
Bus Operation
7-71
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