MPC8572ECVTAULD Freescale Semiconductor, MPC8572ECVTAULD Datasheet - Page 57

• Manufacturer Part Number: MPC8572ECVTAULD
• Description: MPU POWERQUICC III 1023-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8572ECVTAULD

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.333GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Figure 29
Freescale Semiconductor
At recommended operating conditions with BV
Local bus clock to output valid (except LAD/LDP and
LALE)
Local bus clock to data valid for LAD/LDP
Local bus clock to address valid for LAD
Local bus clock to LALE assertion
Output hold from local bus clock (except LAD/LDP and
LALE)
Output hold from local bus clock for LAD/LDP
Local bus clock to output high Impedance (except
LAD/LDP and LALE)
Local bus clock to output high impedance for LAD/LDP
Note:
1. The symbols used for timing specifications herein follow the pattern of t
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.
3. All signals are measured from BV
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
6. t
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured
8. Guaranteed by design.
Table 51. Local Bus General Timing Parameters (BV
(reference)(state)
t
reference (K) goes high (H), in this case for clock one(1). Also, t
t
clock for PLL bypass mode to 0.4 × BV
delivered through the component pin is less than or equal to the leakage current specification.
is programmed with the LBCR[AHD] parameter.
between complementary signals at BV
LBIXKH1
LBK
LBOTOT
provides the AC test load for the local bus.
clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time.
is a measurement of the minimum time between the negation of LALE and any change in LAD. t
symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
for inputs and t
Output
Parameter
(First two letters of functional block)(reference)(state)(signal)(state)
DD
Figure 29. Local Bus AC Test Load
DD
of 1.8 V ± 5% (continued)
/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus
DD
Z
DD
0
/2.
= 50 Ω
of the signal in question for 1.8-V signaling levels.
Symbol
t
t
t
t
t
t
t
t
LBKHOV1
LBKHOV2
LBKHOV3
LBKHOV4
LBKHOX1
LBKHOX2
LBKHOZ1
LBKHOZ2
DD
LBKHOX
= 1.8 V DC)—PLL Enabled (continued)
1
R
L
(First two letters of functional block)(signal)(state)
= 50 Ω
symbolizes local bus timing (LB) for the
Min
0.9
0.9
—
—
—
—
—
—
BV
Max
for outputs. For example,
3.2
3.2
3.2
3.2
2.6
2.6
DD
—
—
/2
Local Bus Controller (eLBC)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
LBK
LBOTOT
Notes
clock
—
3
3
3
3
3
5
5
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