GCIXP1200GA Intel, GCIXP1200GA Datasheet - Page 13

• Manufacturer Part Number: GCIXP1200GA
• Description: IC MPU NETWORK 166MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1200GA

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 166MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 839427

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Specification Update
DMA Write Data Concurrency
A DMA read operation, which transfers data from the PCI bus to SDRAM indicates completion
when the last data has been transferred to the DMA controller, not when it has been written to
SDRAM. This causes the DMA channel to interrupt the process that initiated the DMA transfer.
If the process attempts to read the data just transferred, there is a small possibility that the read
request could precede the pending PCI write request, resulting in stale data being read.
Workaround A
Workaround B
Workaround C
Fixed
I
I
IXP1200 to the SDRAM controller interface. There may be several cycles of latency before the
data is written into SDRAM by the SDRAM controller.
If the IXP1200 StrongARM* Core processor reads the I
the most recently written data and then uses this value to perform a read of that address, there is a
possibility that the IXP1200 StrongARM* core may issue the read request before the PCI write
request has completed. This occurs because the IXP1200 StrongARM* core has higher priority to
the SDRAM than does the PCI.
All entries except the most recently posted entry may be read by the IXP1200 StrongARM* core
immediately. When the most recent data is to be read, ensure that 200 IXP1200 StrongARM* core
clock cycles (i.e., 100 bus clock cycles) have passed since the pointer was read.
Fixed
PCI_DMA Instruction
The Microengine PCI_DMA instruction SDRAM address operand is misaligned.
Incorrect addressing occurs if the address operand is not shifted.
The SDRAM address operand of the PCI_DMA instruction requires a 1-bit right shift for proper
quadword addressing. For example, the address of a Descriptor Pointer located at SDRAM address
0x1000 should be right-shifted 1 bit with the resulting operand value being 0x0800, as follows:
NoFix
2
2
O Inbound Queue pointers are updated when data transfers from the PCI interface of the
O Counter Data Concurrency
Pad the data stream so that the last 4 longwords of data written to the SDRAM are
not valid.
Pad the DMA descriptor table so that the last DMA transaction is a dummy read,
delaying the "DMA_DONE" interrupt until after the last write occur
Stall the process that reads the SDRAM data for approximately 200 clock cycles to
ensure that the PCI read request has been processed.
; fix address of SDRAM Descriptor Pointer
immed[tmp1, 0x1000]
alu[DESC_ADDR,--,B,tmp1,>>1]
; issue DMA request
pci_dma[DESC_ADDR, 0, any_queue]
2
O Inbound Queue pointers to determine
Intel
®
IXP1200 Network Processor
Errata
13