XPC8260CZUHFBC Freescale Semiconductor, XPC8260CZUHFBC Datasheet - Page 4

• Manufacturer Part Number: XPC8260CZUHFBC
• Description: IC MPU POWERQUICC II 480-TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC IIr

Specifications of XPC8260CZUHFBC

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 166MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 480-TBGA
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 133MHz
• Embedded Interface Type: I2C, MII, SPI, TDM, UTOPIA
• Digital Ic Case Style: TBGA
• No. Of Pins: 480
• Rohs Compliant: No
• Family Name: MPC82XX
• Device Core: PowerQUICC II
• Device Core Size: 32b
• Frequency (max): 166MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 480
• Package Type: TBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

Features
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MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 2.0
— 32-bit address decodes with programmable bank size
— Three user programmable machines, general-purpose chip-select machine, and page-mode
— Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local)
— Dedicated interface logic for SDRAM
CPU core can be disabled and the device can be used in slave mode to an external core
Communications processor module (CPM)
— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support
— Interfaces to G2 core through on-chip 32-Kbyte dual-port RAM and DMA controller
— Serial DMA channels for receive and transmit on all serial channels
— Parallel I/O registers with open-drain and interrupt capability
— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
— Three fast communications controllers supporting the following protocols (only FCC1 and
— Two multichannel controllers (MCCs) (only MCC2 on the MPC8255)
— Four serial communications controllers (SCCs) identical to those on the MPC860, supporting
— Two serial management controllers (SMCs), identical to those of the MPC860
pipeline SDRAM machine
for communications protocols
FCC2 on the MPC8255):
– 10/100-Mbit Ethernet/IEEE Std. 802.3® CDMA/CS interface through media independent
– ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5, AAL1,
– Transparent
– HDLC—Up to T3 rates (clear channel)
– Each MCC handles 128 serial, full-duplex, 64-Kbps data channels.Each MCC can be split
– Almost any combination of subgroups can be multiplexed to single or multiple TDM
the digital portions of the following protocols:
– Ethernet/IEEE 802.3 CDMA/CS
– HDLC/SDLC and HDLC bus
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART
– Binary synchronous (BISYNC) communications
– Transparent
– Provide management for BRI devices as general circuit interface (GCI) controllers in time-
interface (MII)
AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 16 K external
connections
into four subgroups of 32 channels each.
interfaces up to four TDM interfaces per MCC
division-multiplexed (TDM) channels
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