MC68020FE33E Freescale Semiconductor, MC68020FE33E Datasheet - Page 39

• Manufacturer Part Number: MC68020FE33E
• Description: IC MICROPROCESSOR 32BIT 132CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68020FE33E

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

3.6 ASYNCHRONOUS BUS CONTROL SIGNALS
The following signals control synchronous bus transfer operations for the
MC68020/EC020. Note that OCS, ECS, and DBEN are implemented in MC68020 and not
implemented in the MC68EC020.
Operand Cycle Start (OCS, MC68020 only)
External Cycle Start (ECS, MC68020 only)
Read/Write (R/ W)
Read-Modify-Write Cycle (RMC)
Address Strobe (AS)
Data Strobe (DS)
3-4
This output signal indicates the beginning of the first external bus cycle for an instruction
prefetch or a data operand transfer. OCS is not asserted for subsequent cycles that are
performed due to dynamic bus sizing or operand misalignment. Refer to Section 5 Bus
Operation for information about the relationship of OCS to bus operation.
OCS is not implemented in the MC68EC020.
This output signal indicates the beginning of a bus cycle of any type. Refer to Section 5
Bus Operation for information about the relationship of ECS to bus operation.
ECS is not implemented in the MC68EC020.
This three-state output signal defines the type of bus cycle. A high level indicates a read
cycle; a low level indicates a write cycle. Refer to Section 5 Bus Operation for
information about the relationship of R/ W to bus operation.
This three-state output signal identifies the current bus cycle as part of an indivisible
read-modify-write operation; it remains asserted during all bus cycles of the read-
modify-write operation. Refer to Section 5 Bus Operation for information about the
relationship of RMC to bus operation.
This three-state output signal indicates that a valid address is on the address bus. The
FC2–FC0, SIZ1, SIZ0, and R /W signals are also valid when AS is asserted. Refer to
Section 5 Bus Operation for information about the relationship of AS to bus operation.
During a read cycle, this three-state output signal indicates that an external device
should place valid data on the data bus. During a write cycle, DS indicates that the
MC68020/EC020 has placed valid data on the bus. During two-clock synchronous write
cycles, the MC68020/EC020 does not assert DS . Refer to Section 5 Bus Operation for
more information about the relationship of DS to bus operation.
Freescale Semiconductor, Inc.
For More Information On This Product,
M68020 USER’S MANUAL
Go to: www.freescale.com
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