MC68EC040RC25A Freescale Semiconductor, MC68EC040RC25A Datasheet - Page 382

• Manufacturer Part Number: MC68EC040RC25A
• Description: IC MPU 32BIT 25MHZ 179-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC040RC25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 179-PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

U1, U0—User Page Attributes
CM—Cache Mode
W—Write Protect
B.3.2 Address Comparison
The following description of address comparison assumes that the ACRs are enabled.
Clearing the E-bit in each ACR independently disables access control, causing the proces-
sor to ignore it.
When an ACU receives a physical address, the privilege mode and the eight high-order bits
of the address are compared to the block of addresses defined by the two ACRs for the cor-
responding ACU. Each block of address space for an ACR contains an S-field, a BASE
ADDRESS field, and an ADDRESS MASK field. The S-field allows for matching either user
or supervisor accesses (or both). Setting a bit in the ADDRESS MASK field causes the cor-
responding bit of the ADDRESS BASE to be ignored in the address comparison and privi-
lege mode. Setting successively higher order bits in the ADDRESS MASK field increases
the size of the block of address space.
The address for the current bus cycle and an ACR address match when the privilege mode
and address bits for each (not including the masked bits) are equal. Each ACR specifies
write protection for the block of address space. Enabling write protection for a block of
address space causes the abortion of write or read-modify-write accesses to the block, and
an access error exception occurs.
By appropriately configuring an ACR, flexible mappings can be specified. For example, to
control access to the user address space, the S-field equals $0, and the ADDRESS MASK
field equals $FF in all four ACRs. To control access to the supervisor address space
($00000000–$0FFFFFFF) with write protection, the BASE ADDRESS field = $0X, the
B-6
MC68EC040
These two bits drive on the user page attribute signals (UPA1 and UPA0). If an external
bus transfer results from the access, U0 and U1 are echoed to the UPA0 and UPA1
signals, respectively. The user can program these bits to support extended addressing,
bus snooping, or other applications. The MC68EC040 does not interpret these bits.
This field selects the cache mode and access serialization for a page as follows:
Detailed information on caching modes is available in Section 4 Instruction and Data
Caches , and information on serialization is available in Section 7 Bus Operation .
This bit indicates if the transparent block is write protected. If set, write and read-modi-
fy-write accesses are aborted as if the R-bit in a table descriptor were clear. Refer to 3.2.2
Descriptors for a description of table descriptors.
00 = Cachable, Write-through
01 = Cachable, Copyback
10 = Noncachable, Serialized
11 = Noncachable
0 = Read and write accesses permitted.
1 = Write accesses not permitted.
REV2.3 (01/31/2000)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
M68040 USER’S MANUAL
MOTOROLA