MC68020FE16E Freescale Semiconductor, MC68020FE16E Datasheet - Page 115
MC68020FE16E
Manufacturer Part Number
MC68020FE16E
Description
IC MICROPROCESSOR 32BIT 132CQFP
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68020EH16E.pdf
(306 pages)
Specifications of MC68020FE16E
Processor Type
M680x0 32-Bit
Speed
166MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-CQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
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State changes occur on the next rising edge of the clock after the internal signal is
recognized as valid. The BG signal transitions on the falling edge of the clock after a state
is reached during which G changes. The bus control signals (controlled by T) are driven
by the processor immediately following a state change when bus mastership is returned to
the MC68020.
State 0, at the top center of the diagram, in which both G and T are negated, is the state
of the bus arbiter while the processor is bus master. Request R and acknowledge A keep
the arbiter in state 0 as long as they are both negated. When a request R is received, both
grant G and signal T are asserted (in state 1 at the top left). The next clock causes a
change to state 2, at the lower left, in which G and T are held. The bus arbiter remains in
that state until acknowledge A is asserted or request R is negated. Once either occurs, the
arbiter changes to the center state, state 3, and negates grant G. The next clock takes the
arbiter to state 4, at the upper right, in which grant G remains negated and signal T
remains asserted. With acknowledge A asserted, the arbiter remains in state 4 until A is
negated or request R is again asserted. When A is negated, the arbiter returns to the
original state, state 0, and negates signal T. This sequence of states follows the normal
sequence of signals for relinquishing the bus to an external bus master. Other states apply
to other possible sequences of combinations of R and A.
The MC68020 does not allow arbitration of the external bus during the read-modify-write
sequence. For the duration of this sequence, the MC68020 ignores the BR input. If
mastership of the MC68020 bus is required during a read-modify-write operation, BERR
must be used to abort the read-modify-write sequence. The bus arbitration sequence
while the bus is inactive (i.e., executing internal operations such as a multiply instruction)
is shown in Figure 5-45.
5-68
M68020 USER’S MANUAL
MOTOROLA
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