MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 350
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MC68MH360AI33L
Manufacturer Part Number
MC68MH360AI33L
Description
IC MPU QUICC 33MHZ 240-FQFP
Manufacturer
Freescale Semiconductor
Specifications of MC68MH360AI33L
Processor Type
M683xx 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Family Name
M68xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
33MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
FQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68MH360AI33L
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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IDMA Channels
7.6.2 IDMA Registers
Each IDMA channel has eight registers that define its specific operation. These registers
include a 32-bit source address pointer register (SAPR), a 32-bit destination address pointer
register (DAPR), an 8-bit function code register (FCR), a 32-bit byte count register (BCR), a
16-bit channel mode register (CMR), an 16-bit channel configuration register (ICCR), an 8-
bit channel status register (CSR), and an 8-bit channel mask register (CMAR). These regis-
ters provide the addresses, transfer count, and configuration information necessary to set
up a transfer. They also provide a means of controlling the IDMA channel and monitoring its
status. All registers can be modified by the CPU32+ core.
For the auto buffer and buffer chaining modes, the RISC controller uses a buffer descriptor
ring to automatically initialize the DAPR, SAPR, and BCR. The buffer descriptor ring resides
in dual-port RAM so that it may be accessed by the RISC controller without bus overhead.
The IDMA channel also includes a 32-bit data holding register (DHR), which is not accessi-
ble to the CPU32+ core and is used by the IDMA for temporary data storage.
7.6.2.1 IDMA CHANNEL CONFIGURATION REGISTER (ICCR). The 16-bit ICCR config-
ures both IDMA channels. It is always readable and writable in the supervisor mode,
although writing is not recommended unless the module is disabled. It is initialized to $0000
at reset.
STP—Stop Bit
7-26
STP
15
• Up to 50 Mbyte/sec Transfer Rates in Single Address Mode and 25 Mbyte/sec in Dual
• 32-Bit Byte Transfer Counters
• 32-Bit Address Pointers That Can Increment or Remain Constant
• Operand Packing and Unpacking for Dual Address Transfers using the Most Efficient
• Supports All Bus-Termination Modes
• Provides Full DMA Handshake for Cycle Steal and Burst Transfers
• Supports Fixed and Rotating Priority Between IDMA Channels
• Buffer Handling Modes: Single Buffer, Auto Buffer, and Buffer Chaining
Address Mode (assuming a 25-MHz system clock)
Techniques
0 = The system clock operates normally within the IDMA.
1 = Stop the system clock to the IDMA channels. This setting is used to conserve pow-
14
er when both IDMAs are unused.
FRZ
13
12
ARBP
11
Freescale Semiconductor, Inc.
For More Information On This Product,
10
MC68360 USER’S MANUAL
Go to: www.freescale.com
ISM
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