MPC8533EVTANG Freescale Semiconductor, MPC8533EVTANG Datasheet - Page 1068
MPC8533EVTANG
Manufacturer Part Number
MPC8533EVTANG
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTANG
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
800MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
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PCI Express Interface Controller
Figure 18-13
18.3.5.1.1
The PCI Express outbound translation address registers, shown in
addresses in the system address space for window hits within the PCI Express outbound address translation
windows. The new translated address is created by concatenating the transaction offset to this translation
address.
Table 18-15
18-20
12–31
0–11
Bits
From Memory
Offset Window 0: 0xC00
Reset
Name
TEA
TA
W
R
Figure 18-14. PCI Express Outbound Translation Address Registers (PEXOTAR n )
describes the fields of the PCI Express outbound translation address registers.
shows the outbound transaction flow.
Window 1: 0xC20
Window 2: 0xC40
Window 3: 0xC60
Window 4: 0xC80
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0
PCI Express Outbound Translation Address Registers (PEXOTAR n )
Translation extended address. System address which indicates the starting point of the outbound translated
address. The translation address must be aligned based on the size field. Corresponds to PCI Express
address bits [43:32] (bit 32 is the lsb).
Translation address. System address which indicates the starting point of the outbound translated address.
The translation address must be aligned based on the size field. This corresponds to PCI Express address
bits [31:12].
Outbound ATMUs
TEA
Figure 18-13. RC Outbound Transaction Flow
Table 18-15. PEXOTAR n Field Descriptions
Prefetchable Memory Limit
Memory or IO Base
Memory or IO Limit
11 12
Primary Side
Memory Base
Prefetchable
All zeros
Description
Figure
TA
18-14, select the starting
Access: Read/Write
Freescale Semiconductor
Secondary Side
31
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