MPC8347EVVAJDB Freescale Semiconductor, MPC8347EVVAJDB Datasheet - Page 28

• Manufacturer Part Number: MPC8347EVVAJDB
• Description: IC MPU PWRQUICC II 672-TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8347EVVAJDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 672-TBGA
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 533MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: TBGA
• No. Of Pins: 672
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Ethernet: Three-Speed Ethernet, MII Management
Figure 13
8.2.3.2
Table 26
28
At recommended operating conditions with LV
PMA_RX_CLK clock period
PMA_RX_CLK skew
RX_CLK duty cycle
RXD[7:0], RX_DV, RX_ER (RCG[9:0]) setup time to rising
PMA_RX_CLK
RXD[7:0], RX_DV, RX_ER (RCG[9:0]) hold time to rising
PMA_RX_CLK
RX_CLK clock rise time V
RX_CLK clock fall time V
Notes:
1. The symbols for timing specifications follow the pattern of t
2. Setup and hold time of even numbered RCG are measured from the riding edge of PMA_RX_CLK1. Setup and hold times
and t
(TR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
the high (H) state or setup time. Also, t
(D) went invalid (X) relative to the t
is based on three letters representing the clock of a particular function. For example, the subscript of t
(T) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). For
symbols representing skews, the subscript SK followed by the clock that is being skewed (TRX).
of odd-numbered RCG are measured from the riding edge of PMA_RX_CLK0.
(first two letters of functional block)(reference)(state)(signal)(state)
provides the TBI receive AC timing specifications.
shows the TBI transmit AC timing diagram.
MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11
TBI Receive AC Timing Specifications
GTX_CLK
Parameter/Condition
TXD[7:0]
TX_EN
TX_ER
IH
IL
(max) to V
(min) to V
Table 26. TBI Receive AC Timing Specifications
TRX
Figure 13. TBI Transmit AC Timing Diagram
IH
IL
(min)
t
(max)
TTXH
DD
TRDXKH
clock reference (K) going to the high (H) state. In general, the clock reference symbol
/OV
DD
t
TTX
symbolizes TBI receive timing (TR) with respect to the time data input signals
of 3.3 V ± 10%.
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
t
Symbol
TRXH
t
t
t
TRDVKH
TRDXKH
TTXF
t
SKTRX
t
t
t
TRXR
TRXF
TRX
/t
TRX
2
1
2
t
TTKHDX
t
TTXR
Min
7.5
2.5
1.5
0.7
0.7
40
TRDVKH
TRX
16.0
Typ
symbolizes TBI receive timing
—
—
—
—
—
—
clock reference (K) going to
Freescale Semiconductor
TRX
represents the TBI
Max
8.5
2.4
2.4
60
—
—
for inputs
Unit
ns
ns
ns
ns
ns
ns
%