MC68030FE20C Freescale Semiconductor, MC68030FE20C Datasheet - Page 243

• Manufacturer Part Number: MC68030FE20C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

7
7.5.1
7-82
: may enter exception processing immediately following the bus cycle, or it
requests instruction words from the bus controller and the instruction cache
The bus error signal can be used to abort the bus cycle and the instruction
When the bus error signal is issued to terminate a bus cycle, the MC68030
being executed. BERR takes precedence over DSACKx or STERM provided
it meets the timing constraints described in MC68030EC/D,
trical Specifications.
unpredictable operation of the MC68030. If BERR remains asserted into the
next bus cycle, it may cause ncorrect operation of that cycle.
fetch, the processor does not take the exception until it attempts to use that
EXAMPLE B:
may defer processing the exception. The instruction prefetch mechanism
before it is ready to execute them. If a bus error occurs on an instruction
instruction word. Should an intervening instruction cause a branch or should
a task switch occur, the bus error exception does not occur.
Bus Errors
A system uses error detection and correction on RAM contents. The de-
signer may:
2. Delay DSACKx until data is verified and assert BERR with or without
3. Return DSACKx prior to data verification. If data is invalid, BERR is
4. Return DSACKx prior to data verification; if data is invalid, assert
1. Delay DSACKx until data is verified; assert BERR and HALT simul-
troller can then correct the RAM prior to or during the automatic
taneously to indicate to the processor to automatically retry the
cessing for software handling of the condition.
asserted on the next clock cycle (case 4). This initiates exception
error cycle (case 5) or, if data is valid, assert DSACKx (case 1).
DSACKx if data is in error (case 3). This initiates exception pro-
processing for software handling of the condition.
BERR and HALT on the next clock cycle (case 6). The memory con-
retry.
If BERR does not meet these constraints, it may cause
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