MPC860ENZQ50D4 Freescale Semiconductor, MPC860ENZQ50D4 Datasheet - Page 64

IC MPU POWERQUICC 50MHZ 357PBGA

MPC860ENZQ50D4

Manufacturer Part Number
MPC860ENZQ50D4
Description
IC MPU POWERQUICC 50MHZ 357PBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC860ENZQ50D4

Processor Type
MPC8xx PowerQUICC 32-Bit
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
MPC8xx
Device Core
PowerQUICC
Device Core Size
32b
Frequency (max)
50MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.465/3.6V
Operating Supply Voltage (min)
2/3.135V
Operating Temp Range
0C to 95C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC860ENZQ50D4
Manufacturer:
MOTOLOLA
Quantity:
784
Part Number:
MPC860ENZQ50D4
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC860ENZQ50D4
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
MPC860ENZQ50D4R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
CPM Electrical Characteristics
11.12 I
Table 26
1
Table 27
1
64
Num
Num
200
200
202
203
204
205
206
207
208
209
210
211
SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3 × pre_scaler × 2).
The ratio SYNCCLK/(BRGCLK/pre_scaler) must be greater than or equal to 4/1.
200
200
202
203
204
205
206
207
208
209
210
211
SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) × pre_scaler × 2).
The ratio SYNCCLK/(BRGCLK / pre_scaler) must be greater than or equal to 4/1.
SCL clock frequency (slave)
SCL clock frequency (master)
Bus free time between transmissions
Low period of SCL
High period of SCL
Start condition setup time
Start condition hold time
Data hold time
Data setup time
SDL/SCL rise time
SDL/SCL fall time
Stop condition setup time
SCL clock frequency (slave)
SCL clock frequency (master)
Bus free time between transmissions
Low period of SCL
High period of SCL
Start condition setup time
Start condition hold time
Data hold time
Data setup time
SDL/SCL rise time
SDL/SCL fall time
Stop condition setup time
provides the I
provides the I
2
C AC Electrical Specifications
2
2
Characteristic
C (SCL < 100 kHz) timings.
C (SCL > 100 kHz) timings.
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
1
1
Table 27. . I
Characteristic
Table 26. I
2
2
C Timing (SCL < 100 kH
C Timing (SCL > 100 kH
Expression
fSCL
fSCL
BRGCLK/16512
1/2(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(40 * fSCL)
Z
Z
)
)
Min
0
0
All Frequencies
Min
250
1.5
4.7
4.7
4.0
4.7
4.0
4.7
All Frequencies
0
0
1/(10 * fSCL)
1/(33 * fSCL)
Freescale Semiconductor
BRGCLK/48
BRGCLK/48
Max
Max
100
100
300
1
Unit
Unit
kHz
kHz
Hz
Hz
μs
μs
μs
μs
μs
μs
ns
μs
ns
μs
s
s
s
s
s
s
s
s
s
s

Related parts for MPC860ENZQ50D4