MPC8241LZQ166D Freescale Semiconductor, MPC8241LZQ166D Datasheet - Page 27

• Manufacturer Part Number: MPC8241LZQ166D
• Description: IC MPU 32BIT 166MHZ PPC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8241LZQ166D

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 166MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Figure 16
Freescale Semiconductor
All values refer to V
Noise margin at the HIGH level for each connected device (including
hysteresis)
Note:
1. The symbols used for timing specifications herein follow the pattern of t
2. As a transmitter, the MPC8245 provides a delay time of at least 300 ns for the SDA signal (referred to the Vihmin of the SCL
3. The maximum t
4. Guaranteed by design
for inputs and t
(I2) with respect to the time data input signals (D) reach the valid state (V) relative to the t
high (H) state or setup time. Also, t
(S) went invalid (X) relative to the t
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
signal) to bridge the undefined region of the falling edge of SCL to avoid the unintended generation of a Start or Stop
condition. When the MPC8245 acts as the I
on SCL and SDA is balanced, the MPC8245 does not cause an unintended generation of a Start or Stop condition. Therefore,
the 300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required
for the MPC8245 as transmitter, the following setting is recommended for the FDR bit field of the I2CFDR register to ensure
both the desired I
clock frequency is 400 KHz and the digital filter sampling rate register (DFFSR bits in I2CFDR) is programmed with its default
setting of 0x10 (decimal 16):
For details on I
for SCL”.
SDRAM Clock Frequency
FDR Bit Setting
Actual FDR Divider Selected
Actual I
provides the AC test load for the I
2
C SCL Frequency Generated
IH
(first two letters of functional block)(reference)(state)(signal)(state)
2
I2DXKL
C frequency calculation, refer to the application note AN2919 “Determining the I
(min) and V
2
C SCL clock frequency and SDA output delay time are achieved. It is assumed that the desired I
has only to be met if the device does not stretch the LOW period (t
Output
MPC8241 Integrated Processor Hardware Specifications, Rev. 10
Parameter
IL
(max) levels (see
Table 13. I
I2SXKL
I2C
clock reference (K) going to the low (L) state or hold time. Also, t
symbolizes I
2
C AC Electrical Specifications (continued)
2
C bus master while transmitting, it drives both SCL and SDA. As long as the load
Figure 16. I
Table
260.4 KHz 148.4 KHz
100 MHz
0x00
384
Z
0
= 50 Ω
12).
2
C.
2
C timing (I2) for the time that the data with respect to the start condition
2
133 MHz
0x2A
896
C AC Test Load
for outputs. For example, t
Symbol
(first two letters of functional block)(signal)(state) (reference)(state)
V
NH
R
L
= 50 Ω
1
0.2 × OV
Min
Electrical and Thermal Characteristics
I2C
OV
I2CL
clock reference (K) going to the
DD
DD
) of the SCL signal.
I2DVKH
/2
2
C Frequency Divider Ratio
I2PVKH
symbolizes I
Max
—
symbolizes I
2
I2C
C timing
2
C SCL
Unit
clock
V
2
C
27