Z8018233ASG Zilog, Z8018233ASG Datasheet - Page 47

• Manufacturer Part Number: Z8018233ASG
• Description: IC 33MHZ STATIC MIMIC 100-LQFP
• Manufacturer: Zilog

Specifications of Z8018233ASG

• Processor Type: Z180
• Features: Smart Peripheral Controller
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Interface Type: UART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When the part is in IDLE mode, the clock oscillator is kept
oscillating, but the clock to the rest of the internal circuit,
including the CLKOUT, is stopped completely. IDLE mode
is exited in a similar way as STANDBY mode, i.e., RESET,
BUS REQUEST or EXTERNAL INTERRUPTS, except that
the 2
asserted eight clock cycles after the exit conditions are
gathered.
STANDBY-QUICK RECOVERY Mode
STANDBY-QUICK RECOVERY mode is an option offered
in STANDBY mode to reduce the clock recovery time in
STANDBY mode from 2
to 2
be used when providing an oscillator as clock source.
To enter STANDBY-QUICK RECOVERY mode:
1. Set D6 and D3 to 1 and 1, respectively.
2. Set the I/O STOP bit (D5 of ICR,
3. Execute the SLEEP instruction.
DS971820600
Zilog
I/O Address = 3FH) to 1.
6
clock cycles (3.2 s at 20 MHz). This feature can only
17
bit wake-up timer is bypassed; all control signals are
Standby/Idle Enable
00 = No Standby
01 = Idle After Sleep
10 = Standby After Sleep
11 = Standby After Sleep
BREXT
0 = Ignore BUSREQ
1 = Standby/Idle Exit
64 Cycle Exit
(Quick Recovery)
Clock Divide
In Standby/Idle
on BUSREQ
0 = XTAL/2
1 = XTAL/1
17
clock cycles (6.5 ms at 20 MHz)
CPU Control Register (CCR) Addr 1FH
D7 D6 D5 D4 D3 D2 D1 D0
0
Figure 51. CPU Control Register
0
P R E L I M I N A R Y
PS009801-0301
0
0
0
When the part is in STANDBY-QUICK RECOVERY mode,
the operation is identical to STANDBY mode except when
exit conditions are gathered, i.e., RESET, BUS REQUEST
or EXTERNAL INTERRUPTS; the clock and other control
signals are recovered sooner than the STANDBY mode.
Note: If STANDBY-QUICK RECOVERY is enabled, the
user must make sure stable oscillation is obtained within
64 clock cycles.
CPU Control Register
The Z8S180 has an additional register which allows the
programmer to select options that directly affect the CPU
performance as well as controlling the STANDBY operating
mode of the chip. The CPU Control Register (CCR) allows
the programmer to change the divide-by-two internal clock
to divide-by-one. In addition, applications where EMI noise
is a problem, the Z8S180 can reduce the output drivers on
selected groups of pins to 25% of normal pad driver
capability which minimizes the EMI noise generated by the
part.
0
0
0
LNPHI
LNAD/DATA
LNCPUCTL
Reserved
0 = Standard Drive
1 = 25% Drive On
0 = Standard Drive
1 = 25% Drive On
0 = Standard Drive
1 = 25% Drive On CPU
EXT .PHI Clock
A19-A0, D7-D0
Control Signals
Z
ILOG
I
NTELLIGENT
Z80182/Z8L182
P
ERIPHERAL
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