Z84C9010VEC Zilog, Z84C9010VEC Datasheet - Page 12

• Manufacturer Part Number: Z84C9010VEC
• Description: IC 10MHZ Z80 KIO XTEMP 84-PLCC
• Manufacturer: Zilog

Specifications of Z84C9010VEC

• Processor Type: Z80
• Features: Serial/Parallel Input/Output, Counter/Timer Circuit
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PS011802-0902
IEI. Interrupt Enable In (input, Active High). This signal is used with Interrupt Enable
Out (IEO) to form a priority daisy chain when there is more than one interrupt-driven
device. A High on this line indicates that no higher-priority device is requesting an inter-
rupt.
IEO. Interrupt Enable Out (output, Active High). This signal is used with Interrupt Enable
In (IEI) to form a priority daisy chain when there is more than one interrupt-driven device.
A High on this line indicates that this device is requesting an interrupt, and that no higher-
priority device, is not requesting an interrupt. A Low blocks any lower-priority devices
from requesting an interrupt.
IORQ. Input/Output Request (input, Active Low). IORQ is used with RD, A
to transfer data between the KIO and the CPU. When IORQ, RD, and CS are Active Low,
the device selected by A
Low, but RD is Active High, the device selected by A
When IORQ and M1 are both Active Low, the KIO may respond with an interrupt vector
from its highest-priority interrupting device.
M1. Machine Cycle 1 (input, Active Low). When M1 and RD are Low, the Z80 CPU
fetches an instruction from memory; the KIO decodes this cycle to determine if the RETI
instruction sequence is being executed. When M1 and IORQ are both active, the KIO
decodes the cycle to be an interrupt acknowledge, and may respond with a vector from its
highest-priority interrupting device.
OSC. Oscillator (output). This output is a reference clock for the oscillator.
PA0–PA7. Port A Bus (bidirectional, tristated). One of the 8-bit ports of the PIO. PA
the least-significant bit of the bus.
PB0–PB7. Port B Bus (bidirectional, tristated). One of the 8-bit ports of the PIO. PB
the least-significant bit of the bus. This port can also supply 1.5mA at 1.5V to drive Dar-
lington transistors.
PC0–PC7. Port C Bus (bidirectional, tristated). PC
These pins are multiplexed between the 8-bit PIA and additional modem control signals
for the serial channels.
RD. Read (input, Active Low). When RD is active, a memory or I/O read operation is in
progress. RD is used with A
CPU.
RESET. Reset (input, Active Low). A Low on this pin forces the KIO into a Reset condi-
tion. This signal must be active for a minimum of three Clock cycles. The KIO resets so
that the PIO ports operate in Mode 1
•
•
•
With handshakes inactive and interrupts disabled
PIA port in Input mode and active
CTC channel counting terminated and interrupts disabled
0
–A
0
3
–A
transfers data to the CPU. When IORQ and CS are Active
3
, CS and IORQ to transfer data between the KIO and
KIO Serial/Parallel Counter Timer
0
is the least-significant bit of the bus.
0
–A
3
is written into by the CPU.
0
–A
3
Z84C90
, and CS
0
0
is
is
7